Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-03-30
2001-11-13
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S298000, C257S304000, C257S310000, C257S758000, C257S765000, C257S768000, C257S769000, C257S770000
Reexamination Certificate
active
06316802
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates in general to the field of semiconductors, and specifically to a semiconductor memory configuration having selection transistors and storage capacitors constructed with at least one multi-layered electrode.
Such integrated semiconductor memory configurations are described in European Patent Application EP 0 514 149A1, where the upper and lower electrodes which bound a dielectric layer at the top and bottom are configured in a multilayered manner. The layer facing the substrate more closely has a high melting point and does not react with the dielectric layer. Titanium, tantalum, tungsten, molybdenum and the like are examples of materials that can be used for the layer facing the substrate more closely. Platinum, palladium, rhodium and aluminum are examples of materials that can be used for the layer configured above the former layer. The upper electrode seated on the dielectric layer consequently has, as shown by an example given in European Patent Application EP 0 514 149 (See
FIG. 1
therein), a lower layer made from titanium and a layer made from platinum seated above the lower layer. The titanium layer is intended to have a thickness of between 10 and 150 nm and the platinum layer a thickness of between 100 and 1200 nm.
Oxide-ceramic dielectrics are being used for the storage capacitor since these dielectrics make it possible to realize comparatively large capacitances in conjunction with a small space requirement. High-&egr;materials such as, for example, (Ba
x
Sr
1−x
TiO
3
) or the ferroelectric material SrBi
2
Ta
2
O
9
are used as oxide-ceramic dielectrics. Because of the high proportion of oxygen in the dielectric and the oxygen atmosphere that is needed during the deposition or during the heat treatment, electrode materials employed heretofore, such as aluminum, polysilicon or suicides, can no longer be used.
Therefore, platinum is being used as a new electrode material, as shown by U.S. Pat. No. 5,330,931 and U.S. Pat. No. 5,466,629, for example.
A satisfactory solution to the patterning of platinum has not been found heretofore. The etching operation is primarily carried out by physical processes using high-energy ions. Furthermore, it has become known to etch platinum anisotropically. However, the etching profiles that can be achieved are still not satisfactory in the case of anisotropic etching. Moreover, platinum has a higher electrical resistivity than, for example, aluminum, namely approximately 10 &mgr;ohms*cm. These disadvantages have made platinum unattractive heretofore as an electrode material even though it has outstanding properties with regard to the junction with ferroelectrics and high-&egr; dielectrics.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide an integrated semiconductor memory configuration that is improved with respect to the previously known semiconductor memory configurations with pure platinum electrodes and is particularly easy to fabricate.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor memory configuration, comprising:
a semiconductor body with selection transistors; and
storage capacitors formed on the semiconductor body, each storage capacitor including an upper electrode, a lower electrode, and a dielectric layer disposed therebetween;
the upper electrode including a platinum layer seated on the dielectric layer and a base metal layer disposed on the platinum layer; the platinum layer having a thickness of up to substantially 10 nm, and the base metal layer having a thickness being greater than the thickness of the platinum layer.
In accordance with an added feature of the invention, the upper electrode extends to other regions of the memory configuration forming an interconnection.
In accordance with an additional feature of the invention, the the thickness of the base metal layer is in a range of greater than substantially 10 nm up to substantially 800 nm.
In accordance with another feature of the invention, the base metal layer is a layer selected from the group consisting of an aluminum layer and a tungsten layer.
In accordance with a further feature of the invention, the lower electrode includes a platinum layer having a thickness and being seated on the dielectric layer, and a base metal layer disposed on the platinum layer and having a thickness being greater than the thickness of the platinum layer.
In accordance with a further added feature of the invention, the semiconductor body has an upper main surface, and the lower electrode, the upper electrode, and the dielectric layer are disposed substantially parallel to the upper main surface of the semiconductor body.
In accordance with a further additional feature of the invention, the the dielectric layer is a layer selected from the group consisting of a ferroelectric layer and a high-&egr; dielectric layer.
In accordance with another added feature of the invention, the platinum layer is a layer produced by a sputtering process.
In accordance with a concomitant feature of the invention, the base metal layer is a layer produced by a CVD process.
Accordingly, at least the upper electrode of the storage capacitor electrodes is constructed in a layered manner with a platinum layer, which faces the dielectric layer, and a base metal layer, which is seated on the platinum layer and has a larger thickness than the platinum layer. By way of example, an aluminum layer or a tungsten layer can be used as the base metal layer.
The platinum layer has a thickness of a few nm, for example up to 10 nm. The base metal layer lying above the platinum layer, on the other hand, is thicker and has a thickness of, preferably, several hundred nm, and preferably up to 800 nm.
The inventive integrated semiconductor memory configuration that has an electrode constructed like a sandwich, has the following advantages over electrodes made of pure platinum or another noble metal:
If the layered electrode structure is used for both electrodes of the storage capacitor, the symmetry of the electrode configuration is preserved by virtue of the thin platinum layer. It is thus possible to avoid disadvantageous effects, such as, for example, imprint or shifting of the hysteresis loop.
It is possible to use a known standard technology in order to apply the base metal to the thin platinum layer. A suitable standard technology is, for example, the CVD deposition of aluminum or tungsten.
The resistivity of the electrode structure according to the invention is smaller as compared to electrodes made of pure platinum. As a result, the upper electrode according to the invention can be used not just for an individual storage capacitor, but rather for an entire memory cell array having a multiplicity of individual storage capacitors, and also as an interconnection in other regions of the integrated semiconductor memory configuration. The advantage of the smaller electrical resistance of the upper electrode is beneficial in this context.
A very thin platinum layer does not make high demands on the etching process with respect to the edge steepness, etching rate, etc. The etching process for platinum is therefore simplified. The other metal applied to the platinum layer can be etched using a standard process and be used as a hard mask for the platinum etching.
With three-dimensional structures having an aspect ratio that is not excessively large, it is possible to use a sputtering process for platinum as long as this process yields at least a slight degree of edge covering. The base metal applied to the platinum layer can be deposited by CVD (chemical vapor deposition), so that the relatively slight difference in thickness in the case of the platinum layer is insignificant.
Therefore, the invention eliminates the necessity of developing a CVD process for platinum.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described he
Bruchhaus Rainer
Engelhardt Manfred
Hartner Walter
Hintermaier Frank
Honlein Wolfgang
Greenberg Laurence A.
Infineon - Technologies AG
Lee Eddie
Lerner Herbert L.
Stemer Werner H.
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