East image processing accelerator for real time image processing

Details East image processing accelerator for real time image processing East image processing accelerator for real time image processing

1988-11-03

1990-06-26

Harkcom, Gary V.

Boots, shoes, and leggings

36472801, G06F 1531

Patent

active

049377744

ABSTRACT:
A modular matrix processor which is capable of configuration as a stand alone symmetrical kernel convolutor or one of plural cascaded asymmetrical kernel convolutors. The module includes coefficient registers and associated multipliers to multiply sequential pixels or words by an appropriate coefficient. A summer, with appropriate input delays, sums the products and provides them to a plurality of FIFO (first in - first out) for storing the sums per row. An adder adds the contents of the summer, FIFO's and cascaded inputs to provide a convolution output P.sub.c. Plural frames may be processed using the pixel input, coefficient input and cascade inputs. Plural modules may be used per row to increase the kernel size as well as the row capacity of the FIFO's.

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Baier et al, "Two-Dimensional Convolution Processor", IBM Tech. Discl. Bull. vol. 26, No. 9, Feb. 1984, pp. 4807-4808.
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"Board Power Chases Mystique, Expense from Image Processing", Leonard, Electronic Design, Sep. 17, 1987 pp. 93-102.
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"Board-Level Image Processors Enter Desktop Arena", Williams, Computer Design, Jun. 1, 1986, pp. 25-30.
"An Economical, Powerful System for Video-Enhanced Microscopy", Maranda, American Laboratory, Apr. 1987.

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