Early triggered ESD MOSFET protection circuit and method...

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

Reexamination Certificate

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Reexamination Certificate

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06958896

ABSTRACT:
An early triggered MOSFET ESD protection circuit based on reduction of the trigger voltage is described. A transient negative voltage is generated and applied to a gate of a MOSFET during a positive ESD event. The instant invention improves ESD performance, and is particularly useful for thin gate oxide of 40 Å and less.

REFERENCES:
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patent: 5852541 (1998-12-01), Lin et al.
patent: 5870268 (1999-02-01), Lin et al.
patent: 5982601 (1999-11-01), Lin
patent: 6043967 (2000-03-01), Lin
patent: 6064556 (2000-05-01), Ravanelli
patent: 6091593 (2000-07-01), Lin
patent: 6304127 (2001-10-01), Lin
patent: 6611025 (2003-08-01), Lin

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