Early noise pulse and long duration, stabilized switching pulse

Static information storage and retrieval – Read/write circuit – Differential sensing

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Details

365 69, 365129, 365193, 365196, G11C 11063

Patent

active

041330501

ABSTRACT:
A large bit size core memory which maximizes usable flux includes at least one array of low drive toroidal magnetic memory cores, a sense-inhibit conductor pair passing through the array in a given direction to inductively couple all cores in the array, a plurality of perpendicular drive conductors, each passing through the array perpendicular to the sense-inhibit conductor pair and inductively coupling a portion of the cores in the array, a plurality of parallel drive conductors, each passing through the array parallel to the sense-inhibit conductor pair and inductively coupling a portion of the cores in the array, and driving and switching circuitry coupled to drive selected a core during a read portion of a memory cycle with a current which rapidly increases to approximately provide the coercive force MMF to the core and then increases relatively slowly toward the full drive current. The resulting core output switching pulse received by a strobed sense amplifier has an early noise component from delta noise and coupling noise and a subsequent logic 1 switching pulse which is extremely stable with respect to normal variations in temperature and drive current, which has a flat, low magnitude peak that satisfies sense amplifier requirements and which is sufficiently delayed to permit attenuation of the noise signals.

REFERENCES:
patent: 3513454 (1970-05-01), Ogrodski
patent: 3905026 (1975-09-01), Sell

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