Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-09-25
2010-06-08
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07735032
ABSTRACT:
A design structure includes a data communication circuit to facilitate communication between a deserializer, responsive to a serial data stream, which puts data onto a parallel bus, and a device that is in data communication therewith. The circuit a deserialization clock that asserts a clock read pulse each time data on the parallel bus is valid. A delay unit asserts a corresponding delayed clock pulse. The delayed clock pulse is delayed from the clock read pulse by a predetermined period. A clock tree repeats the delayed clock pulse and periodically asserts a plurality of end point repeated clock pulses, each of which has a substantially simultaneous leading edge. The predetermined amount of time is selected so as to cause each of the end point repeated clock signals to be asserted when data on the parallel bus is valid, thereby enabling the device to read data from the parallel bus.
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Barrett Wayne M.
Greenfield Todd A.
Bockhop & Associates LLC
International Business Machines - Corporation
Kik Phallaka
Memula Suresh
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