Early high speed serializer-deserializer (HSS)internal...

Details Early high speed serializer-deserializer (HSS)internal... Early high speed serializer-deserializer (HSS)internal...

2006-04-26

2008-11-18

Peyton, Tammara R (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral adapting

C710S034000, C341S100000, C375S354000, C375S371000, C716S030000

Reexamination Certificate

active

07454543

ABSTRACT:
In a method for reading data from a serial data source in a parallel format, data from the serial data source is deserialized by placing a plurality of predefined units of data onto a parallel bus and asserting a deserialization clock when each of the plurality of predefined units is valid on the parallel bus. A delayed clock pulse is generated a predetermined amount of time after each assertion of the deserialization clock. Each delayed pulse is repeated so as to generate an end point repeated clock pulse corresponding to each delayed pulse wherein the predetermined amount of time is an amount of time that ensures that each predefined unit of data on the parallel bus is valid when each end point repeated clock pulse is asserted.

REFERENCES:
patent: 6288656 (2001-09-01), Desai
patent: 7088133 (2006-08-01), Lee et al.
“Synchronous High Speed Serial Interface Clocking,” IBM Technical Disclosure Bulletin, vol. 38 No. 4, Apr. 1995.

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