Electrical computers and digital data processing systems: input/ – Input/output data processing – Data transfer specifying
Reexamination Certificate
2007-09-25
2007-09-25
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Input/output data processing
Data transfer specifying
C710S110000, C710S113000
Reexamination Certificate
active
11464472
ABSTRACT:
A bus architecture includes master devices that are each capable of initiating a data transfer procedure by generating a bus request signal. Each of the master devices is arranged to transmit an address signal to an address input of a multiplexer, to transmit a data signal to a data input of the multiplexer, and to transmit a control signal to a control input of the multiplexer. The control signals may include burst type control signals. The multiplexer is capable of selectively coupling a selected master device chosen from the group consisting of the master devices to a bus. The bus architecture further includes an arbiter arranged to receive the bus request signals as first inputs and arranged to receive the burst type control signals as second inputs, where the burst type control signals are received from an ingress side of the multiplexer.
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AMBA AHB Specification Revision 2.0.
Auve Glenn A.
Cypress Semiconductor Corp.
Stolowitz Ford Cowger LLP
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