Low-voltage reading device in particular for MRAM memory

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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Details

C365S185200, C365S210130, C365S189070

Reexamination Certificate

active

07466595

ABSTRACT:
The invention relates to a circuit for reading a cell of a bit line, including first and second transistors for controlling the bit line and a reference line, respectively, a reference transistor connected to the second control transistor and a write transistor of the reference current connected to the first control transistor, for comparing the current of the bit line and the reference current, characterized in that a first intermediate transistor is connected to the write transistor parallel to the first control transistor, and in that a second intermediate transistor is connected between the gate and the drain of the reference transistor parallel to the second control transistor, and polarization transistors are connected in series, respectively, to the intermediate transistors so as to superimpose a current over the reference current.

REFERENCES:
patent: 5886925 (1999-03-01), Campardo et al.
patent: 5917753 (1999-06-01), Dallabora et al.
patent: 6055187 (2000-04-01), Dallabora et al.
patent: 6600690 (2003-07-01), Nahas et al.
patent: 0 805 454 (1997-11-01), None
French Search Report from corresponding French Application No. 0412194, filed Nov. 17, 2004.

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