Early clock fault detection method and circuit for detecting...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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C714S047300, C714S048000, C713S500000, C713S502000

Reexamination Certificate

active

07089462

ABSTRACT:
An early clock fault detection method and circuit for detecting clock faults in a multiprocessing system provides an error system that can be used to shutdown the multiprocessing system or a processor before errors caused by loss of synchronization between multiple processors can propagate from the processor causing storage or other systems to be corrupted. The detection circuit counts cycles of a high-frequency internal processor clock generated by multiplying an external master clock signal and detects whether or not a predetermined number of clock cycles have elapsed between transitions of the external master clock signal. The detection circuit provides a clock fault output within less than a master clock cycle, which can be used to shut down the processor, system or interconnect between processors, preventing loss or corruption of data before the high-frequency clock can drift enough to cause errors.

REFERENCES:
patent: 5581699 (1996-12-01), Casal et al.

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