Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-07-11
2006-07-11
Torres, Joseph (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
07076716
ABSTRACT:
A method and apparatus for reclaiming bus bandwidth on a full duplex bus. A source node sends a primary packet toward a destination node along a full duplex bus. If the destination node identifies an inability to accept the primary packet, it sends a NAK in the opposite direction along the full duplex bus towards the source node. Upon receiving the NAK, the source node aborts packet transmission of the primary packet which by virtue of the NAK has been identified as futile. Accordingly, the bandwidth, which would have otherwise have been used for the futile packet transmission, can be reclaimed and used for some other purpose.
REFERENCES:
patent: 3866175 (1975-02-01), Seifert, Jr. et al.
patent: 4584684 (1986-04-01), Nagasawa et al.
patent: 4712214 (1987-12-01), Meltzer et al.
patent: 4779274 (1988-10-01), Takahashi et al.
patent: 4831518 (1989-05-01), Yu et al.
patent: 4860292 (1989-08-01), Newman et al.
patent: 4888684 (1989-12-01), Lilja et al.
patent: 4896151 (1990-01-01), Kuranami et al.
patent: 4914653 (1990-04-01), Bishop et al.
patent: 4985890 (1991-01-01), Matsumoto et al.
patent: 5010553 (1991-04-01), Scheller et al.
patent: 5020020 (1991-05-01), Pomfret et al.
patent: 5187780 (1993-02-01), Clark
patent: 5257384 (1993-10-01), Farrand et al.
patent: 5495481 (1996-02-01), Duckwall
patent: 5592536 (1997-01-01), Parkerson et al.
patent: 5664154 (1997-09-01), Purcell et al.
patent: 5802048 (1998-09-01), Duckwall
patent: 5923662 (1999-07-01), Stirling et al.
patent: 5987061 (1999-11-01), Chen
patent: 6012117 (2000-01-01), Traw et al.
patent: 6038234 (2000-03-01), LaFollette et al.
patent: 6154816 (2000-11-01), Steely et al.
patent: 6185184 (2001-02-01), Mattaway et al.
patent: 6208653 (2001-03-01), Ogawa et al.
patent: 6453406 (2002-09-01), Sarnikowski et al.
patent: 2266032 (1993-10-01), None
“IEEE Standard for a High Performance Serial Bus”, IEEE Std. 1394, published by IEEE Inc., New York, NY, Published 1996.
“P1394A Enhancements”, Jan. 3, 1997.
High Speed Serial Interface Protocol, IBM Technical Disclosure Bulletin, Dec. 1991, US, vol. No.: 34, Issue No.: 7A, pp. No.: 355-365, Publication-Date: Dec. 1, 1991.
Derwent-Acc-No.: 1990-049380, Derwent-Week: 199007, 1999.
P1394B Arbitration Acceleration; Teener, Michael D. Johas, Firefly, Inc., 1997, Slides 1-9.
P1394A Enhancements, Jan. 3, 1997, pp. 1-48.
Hauck Jerrold V.
LaFollette David W.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Torres Joseph
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