E.sup.2 prom memory cell

Details E.sup.2 prom memory cell E.sup.2 prom memory cell

1984-01-06

1987-03-31

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

357 235, 365182, G11C 1140

Patent

active

046548254

ABSTRACT:
A five volt only E.sup.2 PROM cell including metal bit read and bit ground column lines and polysilicon word select and program row lines. An interconnected word select and stacked gate transistor serially connect the bit read and bit ground lines. The cell also includes a tunneling structure, disposed below the program row line, for charging or uncharging a floating polysilicon gate in the stacked gate transistor. The bit ground line is disconnected from ground during the charging and uncharging operations.

REFERENCES:
patent: 4203158 (1980-05-01), Frohman-Bentchkdrski et al.
patent: 4266283 (1981-05-01), Perlegos et al.
patent: 4317272 (1981-03-01), Kuo et al.
patent: 4342099 (1982-07-01), Kuo
patent: 4366555 (1982-12-01), Hu
patent: 4379343 (1983-04-01), Moyer
patent: 4477825 (1984-10-01), Yaron et al.
Scherpenberg et al., "Asynchronous Circuits Accelerate Access to 256--K Read--Only Memory", Electronics, vol. 55, No. 11, 6--2--82, pp. 141-145.
Mehrotra, et al., "Oxynitride Film Yields Long--Lived 64--K EE--PROM Cells", Electronics, pp. 118-121, Dec. 1, 1983.
Gupta, et al., "A 5V--Only 16K EEPROM Utilizing Oxynitride Dielectrics and EPROM Redundancy", IEEE Int. Solid--State Circuits Conference, pp. 184-185, Feb. 11, 1982.

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