E.sup.2 PROM device having erase gate in oxide isolation region

Details E.sup.2 PROM device having erase gate in oxide isolation region E.sup.2 PROM device having erase gate in oxide isolation region

1996-03-04

1998-10-06

Wolff, John H.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

H01L 2978

Patent

active

058180826

ABSTRACT:
An E.sup.2 PROM device includes a semiconductor body having source and drain regions and a channel region, with a gate oxide over the channel region and a floating gate over the gate oxide. An oxide isolation region contains a doped polysilicon erase gate, so that erasing of the device takes place by electron flow from the floating gate to the erase gate through a thin oxide portion of the oxide isolation region, at a position spaced from the gate oxide. The inclusion of the erase gate in the oxide isolation region results in smaller overall device size than previously achieved.

REFERENCES:
patent: 4334292 (1982-06-01), Kotecha
patent: 4561004 (1985-12-01), Kuo et al.
patent: 4571705 (1986-02-01), Wada
patent: 4630087 (1986-12-01), Momodomi
patent: 5126809 (1992-06-01), Hirai
patent: 5229632 (1993-07-01), Yoshikawa
patent: 5512505 (1996-04-01), Yuan et al.

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