E.sup.2 PROM cell array including single charge emitting means p

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

365185, 257499, 257390, H01L 2968, H01L 2702, H01L 2710, G11C 1134

Patent

active

052473465

ABSTRACT:
An improved EEPROM having a cell including source and drain diffusions, a channel having a source region and a drain region, a floating gate that is disposed only over the drain region of the channel and has a coupling edge disposed adjacent to the drain diffusion to strongly capacitively couple the floating gate to the drain. During programming the floating gate voltage is increased, due to the capacitive coupling of the floating gate to the drain, which in turn inverts the drain region of the channel. The inversion of the drain region increases the coupling of the floating gate to the drain to increase electron tunneling to program the floating gate. Only three control signals are required to read, program, and erase the cell.

REFERENCES:
patent: 4845538 (1989-07-01), Hazani
patent: 4853895 (1989-08-01), Mitchell et al.
patent: 5047814 (1991-09-01), Hazani

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