Dynamically terminated bus

Details Dynamically terminated bus Dynamically terminated bus

1999-12-20

2001-06-19

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S086000

Reexamination Certificate

active

06249142

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a Dynamically Terminated Bus (“DTB”) that compensates for severe signal integrity problems in traditional multi-drop digital buses.
BACKGROUND
The major performance bottlenecks inherent in Gunning Transceiver Logic (“GTL”) bus designs are well known. As a result, as bus speeds continue to increase, the traditional GTL bus solutions will begin to fail. This is especially true in high speed, multi-processor designs. These failures are inevitable due to the inherent nature of the GTL bus topology. Ideally, a GTL bus is just a long transmission line, with terminations on each end that are pulled up to a Termination Voltage source (“Vtt”). The I/O buffers are then simply coupled directly to the transmission line. In reality, however, each buffer is coupled to the transmission line via a stub. The total stub length can be comprised of several components, such as the chip package, the Printed Circuit Board (“PCB”), a cartridge trace or an interposer. The stubs introduce signal integrity variations and cause timing pushouts. If, however, the stub is short enough so that the timing pushouts are small compared to the available margin, then the timing impact can be tolerated. The problem is that bus speeds are increasing to the point that even short stub lengths are beginning to significantly degrade bus performance.
The inherent signal integrity problems in a GTL bus are caused by the impedance discontinuity of the stub.
FIG. 1A
depicts the circuit topology of an ideal GTL bus with no stub and
FIG. 2A
depicts a realistic GTL topology with a 1″ long stub.
FIG. 1B
shows the ideal waveforms produced by the circuit in FIG.
1
A. In contrast, in
FIG. 2B
, which shows the waveforms produced by the circuit in
FIG. 2A
, notice the ledges on the rising and falling edges of the second waveform seen at point
2
. The timing impacts mentioned above are a direct result of this ledge. If the threshold voltage of a particular buffer is slightly below the ledge and the threshold voltage of another buffer in the same data word is slightly above the ledge, then this introduces a huge amount of timing skew into the system. Furthermore, parasitic inductances and impedance discontinuities may cause the ledge to ring above and below a threshold, which may cause a false trigger of the receiver. For example, if the signal is a clock, the false trigger could cause a system wide failure or, if the signal is on a data line, the false trigger could cause the wrong information to be received.
In
FIG. 1A
, driving agent
10
is pulled up to a Vtt
23
via an on-die termination resistance (“Rtt”)
20
and driving agent
10
is directly coupled to transmission line
16
. Point
2
14
is similarly pulled up to Vtt
24
via Rtt
22
and point
2
14
is directly coupled to transmission line
16
. Point
1
12
is also directly coupled to transmission line
16
.
In
FIG. 2A
, driving agent
10
, point
1
12
and point
2
14
are each configured as in
FIG. 1A
, with the exception that each is now coupled to transmission line
16
by stubs
17
,
18
and
19
, respectively.
The Magnitude of the timing impact is a function of the stub length. In both FIG.
1
A and
FIG. 2A
, the approximate timing impact (“T
impact
”) seen at point
2
14
when driving agent
10
is driving the bus is shown by equation (1).
T
impact
≈
(
2
)
⁢
Length
stub
⁡
(
Er
c
)
(
1
)
Where Er is the dielectric constant that the stub is routed through, c is the speed of light in a vacuum and Length
stub
is the length of the stub. The timing impact is due to the round trip delay of the signal traveling the length of the stub and being reflected back to the bus.
For example, in
FIG. 2B
, the 1.0″ length of stub
17
in
FIG. 2A
introduces approximately a 300 picosecond (“ps”) timing impact, and, in today's high-speed systems, this constitutes more than 100% of the total allowed flight time skew. The voltage level at which the shelf occurs (“V
shelf
”) is dependent on the characteristic impedance of the transmission line (“Zo
pcb
”) and the characteristic impedance of the stub (“Zo
stub
”). Equation (2) is used to approximate the level at which the shelf will occur on the rising edge.
V
shelf
=
V
tt
⁡
(
1
+
(
Zo
stub
&RightDoubleBracketingBar;
⁢
Zo
pcb
)
-
Zo
pcb
(
Zo
stub
&RightDoubleBracketingBar;
⁢
Zo
pcb
)
+
Zo
pcb
)
(
2
)
For realistic ranges of the stub and PCB impedances, this shelf will always be within the threshold range of the buffer for the traditional GTL solution. For example, the traditional GTL solution works with designs such as the Pentium II and other processors which operate at slow enough frequencies so that the excess timing impact due to the stubs can be tolerated. In contrast, the margins in the new high-speed processor designs are too small and the extra timing impact due to the stubs severely breaks the design. In addition, the signal integrity problems caused by the un-terminated stubs exacerbate the inter-symbol interference (“ISI”).
A common belief is that the timing problems associated with stubs on a GTL bus can be compensated for by slowing the edge rates to mask the signal integrity problem. In the slower system designs of the past, this may have been a viable option. In fact, even in today's high-speed designs, some small signal integrity problems may still be masked by slower edge rates. However, this option is not a practical overall design practice, since slower edge rates always translate into increased timing uncertainty. Furthermore, slowing the edge rate is just a temporary patch. As system performance increases and timing budgets decrease, slowing edge rates will cease to be an option due to the timing uncertainty introduced by threshold variation and jitter.
As a result of system bus speeds constantly increasing, traditional GTL and other lower performance bus designs will no longer work. For example, future high speed systems will not work with a traditional GTL bus due to the long stub lengths and associated timing delays introduced by the chip package and the interposer. In the near future, there will be two alternatives for solving the signal integrity problems introduced by stubs. The first alternative is a flow-through chip package that eliminates the stub, unfortunately, this design is very expensive. The second alternative is a different bus design which allows the stubs to be present on the bus. The second alternative minimizes cost and increases performance.
Therefore, an inexpensive and efficient alternative to a GTL bus that helps eliminate the timing pushouts due to the signal integrity problems associated with the traditional GTL topology is needed.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide an apparatus for implementing a high speed digital interface using a dynamically terminated bus (“DTB”) coupled to a plurality of components and a dynamically terminated bus protocol operating to control access to the DTB by the plurality of dynamically configurable bus components.


REFERENCES:
patent: 5821767 (1998-10-01), Osaka et al.
patent: 6023181 (2000-02-01), Penny et al.
patent: 6040714 (2000-03-01), Klein
patent: 6097208 (2000-08-01), Okajima et al.

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