Dynamically synchronizing a processor clock with the leading...

Details Dynamically synchronizing a processor clock with the leading... Dynamically synchronizing a processor clock with the leading...

2006-06-13

2009-02-24

Patel, Nitin C (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S502000

Reexamination Certificate

active

07496779

ABSTRACT:
Systems and methods for detecting a leading edge of a bus clock signal are disclosed herein. One edge detecting system includes a device for providing a bus clock and a processor clock, in which the processor clock is an integer multiple of the bus clock. The device for providing the clocks, however, does not provide a control signal that indicates the location of an edge of the bus clock. The system further includes a clock tree configured to distribute the bus clock and processor clock to multiple destinations, whereby the destinations receive the bus clock and processor clock delayed by an insertion time of the clock tree. The system also includes a processor having a device for detecting the leading edge of the bus clock delayed by the insertion time. Furthermore, a method is disclosed herein. The method includes generating a bus clock and a processor clock without a corresponding control signal, receiving an insertion-delayed version of the bus clock and processor clock, and processing the insertion-delayed bus clock and processor clock to generate a flag signal that indicates the location of a leading edge of the insertion-delayed bus clock.

REFERENCES:
patent: 5729719 (1998-03-01), Gates
patent: 6194927 (2001-02-01), Crowley et al.
patent: 7047433 (2006-05-01), Lin

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