Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-08-22
2009-02-24
Myers, Paul R (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S310000, C710S056000, C711S167000, C711S170000, C711S171000
Reexamination Certificate
active
07496707
ABSTRACT:
A method, data processing system, and PCI Express protocol for enabling high performance IO data transfers for multiple, different IO configurations, which include variable packet sizes and/or variable/different numbers of transactions on the IO link. PCI Express protocol is enhanced to support utilization of counters and dynamically variable queue sizes. In addition to the standard queue entries, several (or a selected number of) dynamically changeable queue entries are provided/reserved and a dynamic queue modification (DQM) utility is provided within the enhanced PCI Express protocol to monitor ongoing, current data transfer and manage when the size(s) of the queue entries are modified (increased or decreased) based on current data traffic transmitting on the PCI Express IO link. The enhanced PCI Express protocol provides an equilibrium point at which many large data packets are transferred efficiently, while imposing a limit on the number of each size of packets outstanding.
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PCI Express Base Specification Revision 1.0a, Apr. 15, 2003—3 pages total.
Freking Ronald E.
Hillier, III Philip R.
Wollbrink Curtis C.
Dillon & Yudell LLP
International Business Machines - Corporation
Misiura Brian T
Myers Paul R
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