Dynamically reconfigurable power-aware, highly scaleable...

Details Dynamically reconfigurable power-aware, highly scaleable... Dynamically reconfigurable power-aware, highly scaleable...

2011-01-18

2011-01-18

Chen, Tse (Department: 2116)

Electrical computers and digital processing systems: support

Reconfiguration

C713S300000, C713S320000

Reexamination Certificate

active

07873823

ABSTRACT:
A large bit width multiplier with multiple copies of a core small bit width multiplier and ROM cells. The present invention provides a power system that trades off processing speed against power dissipation. The present invention reduces power dissipation to about half of the best industry implementation at about half the speed. Its power dissipation is 10% of another industry standard implementation at 1.5 times the speed. The present invention has a gate count that is about twice the gate count for these implementations.

REFERENCES:
patent: 5719800 (1998-02-01), Mittal et al.
patent: 6810482 (2004-10-01), Saxena et al.
patent: 2002/0124219 (2002-09-01), Kuroki
patent: 2003/0217297 (2003-11-01), Gschwind et al.

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