Dynamically reconfigurable logic networks interconnected by fall

Details Dynamically reconfigurable logic networks interconnected by fall Dynamically reconfigurable logic networks interconnected by fall

1998-02-24

2000-08-01

Teska, Kevin J.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

716 16, 703 28, 712 15, 712 17, G06F 1750, H03K 1900

Patent

active

060960914

ABSTRACT:
An integrated circuit comprising a plurality of reconfigurable logic networks, one or more buffers, a configuration control network, and an embedded processor, all comprised as an integral part of the integrated circuit, and a method of operation of the integrated circuit. One or more of the buffers are coupled between two of the plurality of reconfigurable logic networks. The buffers isolate the plurality of reconfigurable logic networks from one another. The integration control network is coupled to each of the plurality of reconfigurable logic networks, and may also be coupled to one or more buffers. The embedded processor is operable to reconfigure one or more of the plurality of reconfigurable logic networks over the configuration control network. The integrated circuit may also comprise a local memory. The local memory is coupled to the embedded processor, and is operable to store data and/or instructions accessible by the embedded processor. A logic configuration library may also be comprised on the integrated circuit. The logic configuration library is coupled to the embedded processor and is further coupled to the configuration control network. The logic configuration library is operable to store one more configurations for the plurality of reconfigurable logic networks. The reconfigurable logic networks preferably include at least a first logic network and a second logic network.

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