Dynamically programmable gate array with multiple contexts

Details Dynamically programmable gate array with multiple contexts Dynamically programmable gate array with multiple contexts

1995-02-10

1998-04-21

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 38, H03K 19177

Patent

active

057421803

ABSTRACT:
An integrated dynamically programmable gate array comprises a two dimensional array of programmable gates. These gates can be implemented as look up tables but hardwired gates with programmable interconnections are also possible. Each one of the gates receives plural input logic signals from plural other gates. Consequently, a broad range of logic combinations are possible. The gates further include locally stored multiple contexts dictating different combinatorial logic operations performed by the gates. The contexts increase the logic operations performable by the gate and the fact that the contexts are locally stored enables better integration and speed. Only a context instruction needs to be distributed among programmable gates. A context signal generator is included that generates a context signal indicating a change in an active one of the contexts. This active context dictates the logic operations of the gates that commonly receive by the signal. Since the contexts information is stored on the gate array, and specifically locally, the context signal can change as fast as every clock cycle of the programmable gate array. To increase functionality, context memory arrays, which store context programming information, are separately addressable so that a new truth table is storable in a first one of the context memory arrays while a truth table of a second one of the context memory arrays is dictating the logic operations performed by the gates. As a result, the functionality of each programmable gate can be increased by increasing the number of available functions for that programmable gate.

REFERENCES:
patent: 4336601 (1982-06-01), Tanaka
patent: 4354228 (1982-10-01), Moore et al.
patent: 4493029 (1985-01-01), Thierbach
patent: 4594661 (1986-06-01), Moore et al.
patent: 4700187 (1987-10-01), Furtek
patent: 4748585 (1988-05-01), Chiarulli et al.
patent: 4758985 (1988-07-01), Carter
patent: 4771285 (1988-09-01), Agrawal et al.
patent: 4791602 (1988-12-01), Resnick
patent: 4870302 (1989-09-01), Freeman
patent: 4879688 (1989-11-01), Turner et al.
patent: 4918440 (1990-04-01), Furtek
patent: 4969121 (1990-11-01), Chan et al.
patent: 4992933 (1991-02-01), Taylor
patent: 5019736 (1991-05-01), Furtek
patent: 5027315 (1991-06-01), Agrawal et al.
patent: 5038386 (1991-08-01), Li
patent: 5081375 (1992-01-01), Pickett et al.
patent: 5260881 (1993-11-01), Agrawal et al.
patent: 5301344 (1994-04-01), Kolchinsky
patent: 5315178 (1994-05-01), Snider
patent: 5336950 (1994-08-01), Popli et al.
patent: 5352940 (1994-10-01), Watson
patent: 5361373 (1994-11-01), Gilson
patent: 5379382 (1995-01-01), Work et al.
patent: 5414377 (1995-05-01), Freidin
patent: 5426378 (1995-06-01), Ong
patent: 5442306 (1995-08-01), Woo
Chen, D.C., et al., "A Reconfigurable Multiprocessor IC for Rapid Prototyping of Algorithmic-Specific High-Speed DSP Data Paths," IEEE Journal of Solid-State Circuits, 27(12):1895-1904 (Dec., 1992).
Denneau, M.M., "The Yorktown Simulation Engine," IEEE 19th Design Automation Conference, pp. 55-59 (1982).
Razdan, R., et al., "A High Performance Microarchitecture with Hardware-Programmable Functional Units," Micro-27Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, pp. 172-180 (Nov. 30-Dec. 2, 1994).
Ling, X.P., "WASMII: A Data Driven Computer on a Virtual Hardware," Keio University, Yokohama, Japan, pp. 1-10. (Apr. 5-7, 1993), FCCM '93, Napa, CA.
Bhat, N.B., "Performance-Oriented Fully Routable Dynamic Architecture for a Field Programmable Logic Device," Memorandum No. UCB/ERL M93/42, University of California, Berkeley (Jun. 1, 1993).
DeHon, A., et al., "DPGA-Coupled Microprocessors: Commodity ICs for the Early 21st Century," IEEE Workshop on FPGAs for Custom Computing Machines, Napa, CA (Apr. 10-13, 1994). *For additional information regarding reference, see Information Disclosure Statement.
Bolotski, M., et al., "Unifying FPGAs and SIMD Arrays," 2nd International ACM/SIGDA Workshop on FPGAs, Berkeley, CA (Feb. 13-15, 1994). *For information regarding reference, see Information Disclosure Statement.
Elliott, D.G., "Computational Ram: A Memory-SIMD Hybrid and its Application to DSP," The Proceedings of the Custom Integrated Circuits Conference, pp. 30.6 1-4 (May 3-6, 1992).
Jones, D, et al., "A Time-Multiplexed FPGA for Logic Emulation," University of Toronto, to appear in CICC, pp. 1-20 (May, 1995).
Lemoine, E., et al., "Run Time Reconfiguration of FPGA for Scanning Genomic DataBases," IEEE Symposium on FPGAs for Custom Computing Machines, FCCM '95, Napa, CA, (Apr. 19-Apr. 21, 1995).
Jones, C., et al., "Issues in Wireless Video Coding Using Run-Time-Reconfigurable FPGAs," IEEE Symposium on FPGAs for Custom Computing Machines, FCCM '95, Napa, CA, (Apr. 19-Apr. 21, 1995).
Li, J., et al., "Routability Improvement Using Dynamic Interconnect Architecture," IEEE Symposium on FPGAs for Custom Computing Machines, FCCM '95, Napa, CA, (Apr. 19-Apr. 21, 1995).
Hadley, J.D., et al., "Design Methodologies for Partially Reconfigured Systems," IEEE Symposium on FPGAs for Custom Computing Machines, FCCM '95, Napa, CA, (Apri. 19-Apr. 21, 1995).
Fried, J., et al., "NAP (No ALU Processor) The Great Communicator," IEEE, 2649(2):383-389 (1988).
Yeung, A.K., "A 2.4 GOPS Reconfigurable Data-Driven Multiprocessor IC for DSP," Dept. of EECS, University of California, Berkeley, pp. 1-14, (Feb. 14, 1995) ISSCC '95, pp. 108-109.
Hawley, D., "Advancd PLD Architectures," In FPGAs, W R Moore & W Luk (eds.) (UK: Abingdon EE&CS Books), pp. 11-23 (1991).

Affiliated with

Also associated with

Rating

Dynamically programmable gate array with multiple contexts does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamically programmable gate array with multiple contexts, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamically programmable gate array with multiple contexts will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2061415