Dynamically managing thermal levels in a processing system

Electrical computers and digital processing systems: support – Computer power control – Power conservation

Reexamination Certificate

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Details

C713S300000, C713S322000, C718S102000

Reexamination Certificate

active

07934110

ABSTRACT:
A technique to dynamically maintain the thermal levels of a plurality of cores of a processing system by interleave core hopping with throttling techniques. The interleaving logic may transfer execution of threads from a hot core to a cold if core hopping is applicable. Core hopping may be applicable if there exist a cold core to which the execution of threads can be assigned to from a hot core and if the rate of occurrence of core hopping is within an allowable rate value. The interleaving logic may apply throttling techniques if core hopping is not applicable. The throttling techniques may throttle the throttling parameters, which may comprise voltage, frequency, and micro-architecture throttling parameters provided to the hot core if the core hopping is not applicable.

REFERENCES:
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patent: 2002/0043563 (2002-04-01), Ishii
patent: 2005/0071701 (2005-03-01), Luick
patent: 2008/0022076 (2008-01-01), Krieger et al.
patent: 2008/0115010 (2008-05-01), Rothman et al.
patent: 2008/0236175 (2008-10-01), Chaparro Monferrer et al.
patent: 2008/0310099 (2008-12-01), Monferrer et al.
patent: 2009/0064164 (2009-03-01), Bose et al.

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