Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-03-23
2009-12-01
Shah, Kamini S (Department: 2128)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C714S030000, C714S738000, C714S739000, C714S742000, C702S118000, C717S124000, C703S022000
Reexamination Certificate
active
07627843
ABSTRACT:
The input for a test generator is a plurality of test templates, each of which typically aims at covering a specific verification task. Test templates direct the production of distinct transactions, which are the atomic functional building blocks of the design-under-verification. Test templates directed to different hardware functions of the scenario are dynamically interleaved. In this way several transactions are combined together in complex statements in order to achieve a complex test scenario. The transactions are submitted to the test generator, which generates test cases, in which the different hardware functions of the scenario are exercised in combinations. Variation among the test cases is achieved through a large number of random decisions made during the generation process.
REFERENCES:
patent: 5774358 (1998-06-01), Shrote
patent: 5809108 (1998-09-01), Thompson et al.
patent: 5940472 (1999-08-01), Newman et al.
patent: 5978940 (1999-11-01), Newman et al.
patent: 6002869 (1999-12-01), Hinckley
patent: 6002871 (1999-12-01), Duggan et al.
patent: 6212667 (2001-04-01), Geer et al.
patent: 6453276 (2002-09-01), Bauman
patent: 6574578 (2003-06-01), Logan
patent: 6757882 (2004-06-01), Chen et al.
patent: 6775824 (2004-08-01), Osborne et al.
patent: 6785876 (2004-08-01), Takemura
patent: 6871298 (2005-03-01), Cavanaugh et al.
patent: 6993747 (2006-01-01), Friedman
patent: 7000224 (2006-02-01), Osborne et al.
patent: 7027971 (2006-04-01), Gabele et al.
patent: 7133816 (2006-11-01), Adir et al.
patent: 7231616 (2007-06-01), Mohanty et al.
patent: 7299382 (2007-11-01), Jorapur
patent: 7434101 (2008-10-01), Adir et al.
patent: 7496876 (2009-02-01), Selvam
patent: 2002/0029377 (2002-03-01), Pavela
patent: 2003/0130813 (2003-07-01), Adir et al.
patent: 2003/0130831 (2003-07-01), Adir
patent: 2003/0204784 (2003-10-01), Jorapur
patent: 2004/0078742 (2004-04-01), Emek et al.
patent: 2004/0133858 (2004-07-01), Barnett et al.
patent: 2004/0143819 (2004-07-01), Cheng et al.
patent: 2004/0261050 (2004-12-01), Broberg et al.
patent: 2005/0144529 (2005-06-01), Gotz et al.
patent: 2005/0203720 (2005-09-01), Lagoon et al.
patent: 2006/0212756 (2006-09-01), Emek et al.
patent: 2008/0126070 (2008-05-01), Copty et al.
patent: 2008/0177968 (2008-07-01), Emek et al.
R. Emek, Y. Naveh, “Scheduling of Transactions for System-Level Test Case Generation” 2003 IEEE.
N. Malik, S. Roberts, A. Pita, and R. Dobson, “Automation: an Autonomous Coverage Multiprocessor System Verification Environment” Feb. 26, 2004.
E. Bin. R. Emek, G. Shurek, A. Ziv, “Using a constraint satisfaction formulation and solution techniques for random test program generation” IBM Systems Journal, vol. 41, No. 3, 2002.
A. E. Ilowe, A. V.Mayriiauser, R. T. Mraz, “Test Case Generation as an Al Planning Problem”, 1991.
R. Emek, I. Jaeger, Y. Katz, and Y. Naveh, “Quality Improvement Methods for System-level Stimuli Generation”, pp. 1-3, 2004 IEEE.
L. Fournier, Y. Arbetman, M. Levinger, “Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator”, pp. 1-8, Functional Verification Methodology, Dec. 17, 1998.
R. Emek, I. Jaeger, Y. Katz, and Y. Naveh, “Quality Improvement Methods for System-level Stimuli Generation”, IEEE International Conference on Computer Design, 2004.
Grinwald, R. et al., “User Defined Coverage—A Tool Supported Methodology for Design Verification”, Proceedings of 38th Design Automation Conference (DAC98), Jun. 15-19, 1998, pp. 158-163.
Lichtenstein, Y. et al, “Model Based Test Generation for Processor Verification”, Innovative Applications of Artificial Intelligence (IAAI), AAAI Press, 1994.
Lewin, Daniel et al., “Constraint Satisfaction for Test Program Generation”, Int. Phoenix Conference on Computers and Communications, Mar. 1995.
Aharon, A. et al., “Test Program Generation for Functional Verification of PowerPC Processors in IBM”, 32nd Design Automation Conference, San Francisco, Jun. 1995, pp. 279-285.
Emek, Roy et al., “X-Gen: A Random Test-Case Generator for Systems and SoCs”, IEEE International High Level Design Validation and Test Workshop (HLDVT), pp. 145-150, Oct. 2002, Cannes, France.
Dozorets Igor
Emek Roy
Gupta Sanjay
Jaeger Itai
McConville Lawrence Allyn
Gebresilassie Kibrom K
International Business Machines - Corporation
Shah Kamini S
LandOfFree
Dynamically interleaving randomly generated test-cases for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dynamically interleaving randomly generated test-cases for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamically interleaving randomly generated test-cases for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4114963