Dynamically coupled metrology and lithography

Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing

Reexamination Certificate

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Details

C700S121000, C438S014000, C716S030000

Reexamination Certificate

active

10773665

ABSTRACT:
Methods for determining tolerances are disclosed that can be used for determining whether a lot of semiconductor wafers needs to be reworked. Overlay tolerance, critical dimension tolerance and a dynamic line edge placement tolerance are determined using error measurements that are taken from sample wafers in the lot, giving tolerances that reflect the error state of that particular lot of semiconductor wafers.

REFERENCES:
patent: 5701013 (1997-12-01), Hsia et al.
patent: 5952132 (1999-09-01), King et al.
patent: 6127075 (2000-10-01), Hsu
patent: 6440759 (2002-08-01), Commons et al.
patent: 2003/0033046 (2003-02-01), Yoshitake et al.
patent: 2003/0087192 (2003-05-01), Gau et al.
patent: 2003/0115558 (2003-06-01), Conrad et al.

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