Dynamically controlled output multiplexer circuits in a...

Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...

Reexamination Certificate

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C326S041000

Reexamination Certificate

active

07746104

ABSTRACT:
A programmable integrated circuit includes a plurality of interconnected logic blocks, each including a logic circuit and an output multiplexer circuit. The output multiplexer circuit includes a first multiplexer having first and second data inputs respectively coupled to first and second outputs of the logic circuit, a select input coupled to an output of another logic block, and a first data output. A second output multiplexer may also have first and second data inputs respectively coupled to the first and second outputs of the logic circuit, a select input coupled to the output of the another logic block, and a second data output. The output multiplexer circuit is programmably coupled, in one of a plurality of operating modes, to provide an output token with the first output of each logic block only when the output multiplexer circuit of the logic block receives tokens indicating valid new data on each of the first, second, and select inputs of the circuit.

REFERENCES:
patent: 5208491 (1993-05-01), Ebeling et al.
patent: 5367209 (1994-11-01), Hauck et al.
patent: 6150838 (2000-11-01), Wittig et al.
patent: 6184712 (2001-02-01), Wittig et al.
patent: 6208163 (2001-03-01), Wittig et al.
patent: 6486709 (2002-11-01), Sutherland et al.
patent: 6522170 (2003-02-01), Durham et al.
patent: 6590424 (2003-07-01), Singh et al.
patent: 6708193 (2004-03-01), Zeng
patent: 6958627 (2005-10-01), Singh et al.
patent: 7157934 (2007-01-01), Teifel et al.
patent: 7196543 (2007-03-01), Young et al.
patent: 7202698 (2007-04-01), Bauer et al.
patent: 7274211 (2007-09-01), Simkins et al.
patent: 7417456 (2008-08-01), Verma et al.
patent: 7467175 (2008-12-01), Simkins et al.
patent: 7467177 (2008-12-01), Simkins et al.
patent: 7472155 (2008-12-01), Simkins et al.
patent: 7480690 (2009-01-01), Simkins et al.
patent: 7504851 (2009-03-01), Manohar et al.
patent: 7505304 (2009-03-01), Manohar et al.
patent: 2005/0127944 (2005-06-01), Lewis et al.
patent: 2005/0144210 (2005-06-01), Simkins et al.
patent: 2006/0164119 (2006-07-01), Nowak-Leijten
patent: 2006/0190516 (2006-08-01), Simkins et al.
patent: 2006/0195496 (2006-08-01), Vadi et al.
patent: 2006/0206557 (2006-09-01), Wong et al.
patent: 2006/0212499 (2006-09-01), New et al.
patent: 2006/0230092 (2006-10-01), Ching et al.
patent: 2006/0230093 (2006-10-01), New et al.
patent: 2006/0230094 (2006-10-01), Simkins et al.
patent: 2006/0230095 (2006-10-01), Simkins et al.
patent: 2006/0230096 (2006-10-01), Thendean et al.
patent: 2006/0288069 (2006-12-01), Simkins et al.
patent: 2006/0288070 (2006-12-01), Vadi et al.
patent: 2007/0256038 (2007-11-01), Manohar
patent: 2008/0168407 (2008-07-01), Manohar
U.S. Appl. No. 12/417,007, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/417,010, filed Apr. 2, 2009, Young.
U.S. Appl. No. 12/417,012, filed Apr. 2, 2009, Young.
U.S. Appl. No. 12/417,013, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/417,015, filed Apr. 2, 2009, Young.
U.S. Appl. No. 12/417,018, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/417,020, filed Apr. 2, 2009, Gaide et al.
U.S. Appl. No. 12/417,023, filed Apr. 2, 2009, Gaide et al.
U.S. Appl. No. 12/417,033, filed Apr. 2, 2009, Gaide et al.
U.S. Appl. No. 12/417,036, filed Apr. 2, 2009, Gaide et al.
U.S. Appl. No. 12/417,040, filed Apr. 2, 2009, Gaide et al.
U.S. Appl. No. 12/417,043, filed Apr. 2, 2009, Gaide et al.
U.S. Appl. No. 12/417,046, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/417,048, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/417,051, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/417,054, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/417,057, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/174,905, filed Jul. 17, 2009, Young.
U.S. Appl. No. 12/174,926, filed Jul. 17, 2008, Young.
U.S. Appl. No. 12/174,945, filed Jul. 17, 2008, Young.
U.S. Appl. No. 12/174,956, filed Jul. 17, 2008, Young.
U.S. Appl. No. 12/174,972, filed Jul. 17, 2008, Young et al.
Achronix Semiconductor Corp.,Introduction to Achronix FPGAs; WP001 Rev. 1.6, Aug. 7, 2008, pp. 1-7, available from Achronix Semiconductor Corp., San Jose, California, USA.
Achronix Semiconductor Corp.,Speedster FPGA Family, PB001 v3.5, copyright 2008, pp. 1-2, available from Achronix Semiconductor Corp., San Jose, California, USA.
Asato, Creighton et al., “A Data-Path Multiplier with Automatic Insertion of Pipeline Stages,”IEEE Journal of Solid-State Circuits, Apr. 1990, pp. 383-387, vol. 25, No. 2.
Borriello, F. et al., “The Triptych FPGA Architecture,”IEEE Transactions on Very Large Scale Integration(VLSI)Systems, Dec. 1990, pp. 491-501, vol. 3, No. 4.
Callaway, Thomas K., “Optimizing Arithmetic Elements for Signal Processing,”Proc. of the 1992 Workshop on VLSI Signal Processing, Oct. 28-30, 1992, vol. V, pp. 99-100, Napa Valley, California, USA.
Habibi, I. et al., “Fast Multipliers,”IEEE Transactions on Computers, Feb. 1970, pp. 153-157, vol. C-19, Issue 2.
Halfhill, Tom, “Ambric's New Parallel Processor,”Microprocessor Report, Oct. 10, 2006, pp. 1-9, available from In-Stat, 2055 Gateway Place, San Jose, California, USA, or http;//www.mpronline.com.
Hauck, Scott et al., “Montage: An FPGA for Synchronous and Asynchronous Circuits,”Field-Programmable Gate Arrays: Architecture and Tools for Rapid Prototyping, 1999, pp. 44-51, publ. by Springer Verlag, Berlin, Germany.
Hauck, Scott et al., “An FPGA for Implementing Asynchronous Circuits”IEEE Design and Test of Computers, Fall 1994, pp. 60-69, vol. 11, No. 3.
Hauck, Scott, “Asynchronous Design Methodologies: An Overview,”Proc. of the IEEE, Jan. 1995, pp. 69-93, vol. 83, No. 1.
Hauser, John,The Garp Architecture, Oct. 1997, pp. 1-56, University of California at Berkeley, USA.
Huang, Randy,Hardware-Assisted Fast Routing for Runtime Reconfigurable Computing, Fall 2004, pp. 1-43, dissertation submitted to University of California at Berkeley, USA.
Jain, Surendra K. et al., “Efficient Semisystolic Architectures for Finite-Field Arithmetic”IEEE Transactions on Very Large Scale Integration(VLSI)Systems, Mar. 1998, pp. 101-113, vol. 6, No. 1.
Maden, B. et al., “Parallel Architectures for High Speed Multipliers”Proc. of the 1989 IEEE International Symposium on Circuits and Systems, May 8-11, 1989, pp. 142-145, Portland, Oregon.
Martin, Alain et al., “The Design of an Asynchronous Microprocessor,”Proc. Decennial Caltech Conference on VLSI, Mar. 20-22, 1989, pp. 1-23.
Meier, Pascal C. H. et al., “Exploring Multiplier Architecture and Layout for Low Power”Proc. of the 1996 IEEE Custom Integrated Circuits Conference, May 5-8, 1996, pp. 513-516.
Muhammad, Khurram et al., “Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design,”Proc. of the 1999 IEEE International Conference on Computer Design, Oct. 10-13, 1999, pp. 230-235, Austin, Texas, USA.
Panato, Alex et al., “Design of Very Deep Pipelined Multipliers for FPGAs,”Proc. of the Design, Automation and Test in Europe Conference and Exhibition Designers' Forum, Feb. 16-20, 2004, pp. 52-57, vol. 3, Paris, France.
Payne, R., “Asynchronous FPGA Architecture,”IEE Proc.-Comput. Digit. Tech., Sep. 1996, pp. 282-286, vol. 143, No. 5.
Sparso, J.,Asynchronous Circuit Design—A Tutorial, copyright 2006, pp. 1-179, available from the Technical University of Denmark, Kgs. Lyngby, Denmark.
Teifel, John et al., “Highly Pipelined Asynchronous FPGAs,”Proc. of the 2004 ACM-SIGDA International Symposium on Field Programmable Gate Arrays, Feb. 22-24, 2004, pp. 133-142, Monterey, California, USA.
Tsu, William et al., “High-Speed, Hierarchical Synchronous Reconfigurable Array,”Proc. of the 1999 ACM/SIGDA 7thInternational Symposium on Field Programmable Gate Arrays, Feb. 21-23, 1999, pp. 125-134, Monterey, California, USA.
Wikipedia, “C-element,” downloaded Jul. 17, 2008 from http://en.wikipedia.org/C-element, pp. 1-2.
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