Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2001-03-30
2003-02-04
Portka, Gary J (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S106000, C711S128000
Reexamination Certificate
active
06516399
ABSTRACT:
FIELD OF THE INVENTION
The present device relates generally to semiconductor devices and, more particularly, to semiconductor device memory.
BACKGROUND OF THE INVENTION
In recent years, the semiconductor industry has realized tremendous advances in technology which have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. In addition, the increased speed of operation has resulted in a widespread demand for the use of products that incorporate semiconductor devices, such as computers, cellular phones and other electronic products.
For example, in semiconductor ASIC devices there is logic implemented to track certain events that are then used to either enforce pre-chosen algorithm or policies. Some examples of these include Arbiters that decide the type of access to grant to a particular agent based on a policy Cache controller that maps a much bigger slow memory space into a small fast memory based on certain mapping scheme TLB's that map a bigger virtual space into a smaller physical memory space based on a mapping scheme.
In the case of memory controllers using multiple internal bank organization, page tables track open pages. Due to the large number of memory banks that exist in these and other applications, typical page tables can not store every possible page open, and page table designs have had to compromise between the number of entries that can be stored and the time required to access data stored in the page table.
SUMMARY OF THE INVENTION
The present invention makes possible dynamic configuration of memory page tables, and addresses problems stated in the Background hereinabove. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention a memory device includes a page table having a plurality of pages, each page having a multitude of memory storage locations adapted to store data. The page table is dynamically configurable to at least two organizations. A controller is adapted to track memory requests and to configure the page table to one of the at least two organizations during a memory refresh cycle. The configuration of the page table is effected in response to the tracked memory requests. In this manner, difficulties associated with memory storage, including those described hereinabove in the Background are addressed, and the need to compromise between the number of entries that can be stored and the time required to access data stored in the page table can be reduced.
According to a more specific example embodiment of the present invention, a controller is adapted to configure the page table to at least one of a first organization and a second organization. The first organization is characterized by fewer data management conflict misses relative to the second organization, and the second organization is characterized by a faster data access time relative to the first organization.
In another example embodiment of the present invention, a method is used for storing data in a memory. The method includes storing data in a page table having a plurality of pages, wherein each page has a multitude of memory storage locations adapted to store data. The page table is dynamically configurable to at least two organizations. Memory requests are tracked, and the page table is configured to one of the at least two organizations during a memory refresh cycle. The configuration is effected in response to the tracked memory requests.
The above summary is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.
REFERENCES:
patent: 5752275 (1998-05-01), Hammond
patent: 5978888 (1999-11-01), Arimilli et al.
patent: 6330639 (2001-12-01), Fanning et al.
Koninklijke Philips Electronics , N.V.
Portka Gary J
Zawilski Peter
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