Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
2006-12-22
2008-11-18
Le, Don P (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S046000
Reexamination Certificate
active
07453285
ABSTRACT:
A dynamically configurable logic gate includes an input summer for receiving a first input signal and a second input signal to generate a summed input signal. Further the dynamically configurable logic gate includes a nonlinear element that applies a nonlinear function to the summed input signal to produce a nonlinear output signal. The dynamically configurable logic gate output signal corresponds to one of a plurality of different logic gates responsive to adjusting the summed input signal and/or the nonlinear function. In another embodiment, the dynamically configurable logic gate includes feedback to one of the inputs. The dynamically configurable logic gate receives the two inputs and operates as one of a plurality of different logic gate types so as to produce an output signal that corresponds to a memory latch according to a selection of the control signal. An array structure of dynamically configurable logic elements is also disclosed.
REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5291555 (1994-03-01), Cuomo et al.
patent: 5745655 (1998-04-01), Chung et al.
patent: 5809009 (1998-09-01), Matsuoka et al.
patent: RE35977 (1998-12-01), Cliff et al.
patent: 6025735 (2000-02-01), Gardner et al.
patent: 6066961 (2000-05-01), Lee et al.
patent: 6466051 (2002-10-01), Jones et al.
patent: 6876232 (2005-04-01), Yoo
patent: 7096437 (2006-08-01), Ditto et al.
patent: 7218139 (2007-05-01), Young et al.
patent: 2003/0225714 (2003-12-01), Catalasan
patent: 2004/0036636 (2004-02-01), Mai et al.
patent: 2005/0108306 (2005-05-01), Catalasan
Murali et al., “Realization of the Fundamental NOR Gate using a Chaotic Circuit,” Physical Review 68:1-5, 2003.
Murali et al., “Implementation of NOR Gate by a Chaotic Chua's Circuit,” Unpublished, 2003.
Munakata et al., “Chaos Computing: Implementation of Fundamental Logical Gates by Chaotic Elements,” IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications 49:1629-1633, 2002.
Murali et al., “Experimental Chaos Computing,” Submitted to IEEE Trans. On Circuits and Systems, in 2003.
Kiel Steven Lee
Krening Douglas Norman
Lehman Lark Edward
Schneiderwind Michael Joseph
Chaologix, Inc.
Fleit Gibbons Gutman Bongini & Bianco P.L.
Gibbons Jon A.
Le Don P
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