Dynamically adjusting operation of a circuit within a...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

Reexamination Certificate

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C326S087000

Reexamination Certificate

active

07573288

ABSTRACT:
Systems and methods for dynamically adjusting operation of a circuit within a semiconductor device are described herein. At least some illustrative embodiments include a system that includes a matching circuit including a first plurality of switching devices coupled to each other in parallel and not coupled in parallel to a resistive device, a driver circuit including a plurality of driver devices (the driver circuit adjusted based upon which of the switching devices are enabled), and processing logic that couples to the matching and driver circuits. The processing logic derives a binary value indicative of which of the switching devices are to be enabled, the binary value reflecting one or more process corners associated with the switching devices, and not reflecting one or more process corners associated with the resistive device. The processing logic further maps the binary value to a control value used to adjust the driver circuit.

REFERENCES:
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Farrell, T., “Core architecture doubles mem date rate”; EE Times Asia; Dec. 16, 2005; EE Times Asia; eMedia Asia Ltd.; New York, NY; http://www.eetasia.com/MUL—technical-articles—32—TA.HTM.
Allan, G., “start: The outlook for DRAMs in consumer electronics”; EDA Tech Forum; Jan. 12, 2007; CMP Media LLP; Manhasset, NY; http://edadesignline.com/196900432;jsessionid=IP1AF51SS4QEEQSNDLPCKHSCJUNN2JVN?printableArticle=true.

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