Computer graphics processing and selective visual display system – Computer graphics display memory system – Memory allocation
Reexamination Certificate
2005-12-13
2005-12-13
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Memory allocation
C345S539000, C345S503000
Reexamination Certificate
active
06975322
ABSTRACT:
A graphics system includes a hardware accelerator and a frame buffer. The frame buffer includes a sample storage area and a double-buffered display pixel area. The hardware accelerator is operable to (a) render a stream of primitives into samples, (b) store the samples into the sample storage area of the frame buffer, (c) read the samples from the sample storage area, (d) filter the samples to generate pixels, and (e) store the pixels into a first buffer of the display pixel area of the frame buffer. Furthermore, the hardware accelerator is operable to perform (a), (b), (c), (d) and (e) one or more times on one or more corresponding streams of primitives to complete a frame of an animation before passing control of the first buffer to a video output processor.
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European Search Report, 03251516.5-2218, mailed Nov. 23, 2004.
Brightwell Mark K.
Hood Jeffrey C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Sun Microsystems Inc.
Tung Kee M.
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