Dynamically adjustable termination impedance control techniques

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C326S021000, C326S023000, C326S026000, C326S077000

Reexamination Certificate

active

06888370

ABSTRACT:
The on-chip impedance termination circuits can be dynamically adjusted to match transmission line impedance values. A network of termination resistors on an integrated circuit provides termination impedance to a transmission line coupled to an IO pin. The termination resistors are coupled in series and in parallel with each other. Pass gates are coupled to the resistors. The pass gates are individually turned ON or OFF to couple or decouple resistors from the transmission line. Each pass gate is set to be ON or OFF to provide a selected termination resistance value to the transmission line. The termination resistance of the resistor network can be increased or decreased to match the impedance of different transmission lines. The termination resistance can also be varied to compensate for changes in the resistors caused by temperature variations on the integrated circuit or other factors.

REFERENCES:
patent: 4719369 (1988-01-01), Asano et al.
patent: 4954729 (1990-09-01), Urai
patent: 5111081 (1992-05-01), Atallah
patent: 5134311 (1992-07-01), Biber et al.
patent: 5164663 (1992-11-01), Alcorn
patent: 5179300 (1993-01-01), Rolandi et al.
patent: 5359235 (1994-10-01), Coyle et al.
patent: 5374861 (1994-12-01), Kubista
patent: 5592510 (1997-01-01), Van Brunt et al.
patent: 5602494 (1997-02-01), Sundstrom
patent: 5623216 (1997-04-01), Penza et al.
patent: 5726582 (1998-03-01), Hedberg
patent: 5726583 (1998-03-01), Kaplinsky
patent: 5764080 (1998-06-01), Huang et al.
patent: 5864715 (1999-01-01), Zani et al.
patent: 5939896 (1999-08-01), Hedberg
patent: 5955911 (1999-09-01), Drost et al.
patent: 5970255 (1999-10-01), Tran et al.
patent: 6008665 (1999-12-01), Kalb et al.
patent: 6026456 (2000-02-01), Ilkbahar
patent: 6037798 (2000-03-01), Hedberg
patent: 6049255 (2000-04-01), Hagberg et al.
patent: 6064224 (2000-05-01), Esch, Jr. et al.
patent: 6087847 (2000-07-01), Mooney et al.
patent: 6097208 (2000-08-01), Okajima et al.
patent: 6100713 (2000-08-01), Kalb et al.
patent: 6118310 (2000-09-01), Esch, Jr.
patent: 6147520 (2000-11-01), Kothandaraman et al.
patent: 6154060 (2000-11-01), Morriss
patent: 6157206 (2000-12-01), Taylor et al.
patent: 6181157 (2001-01-01), Fiedler
patent: 6236231 (2001-05-01), Nguyen et al.
patent: 6252419 (2001-06-01), Sung et al.
patent: 6329836 (2001-12-01), Drost et al.
patent: 6356106 (2002-03-01), Greeff et al.
patent: 6362644 (2002-03-01), Jeffery et al.
patent: 6366128 (2002-04-01), Ghia et al.
patent: 6411126 (2002-06-01), Tinsley et al.
patent: 6414512 (2002-07-01), Moyer
patent: 6424169 (2002-07-01), Partow et al.
patent: 6433579 (2002-08-01), Wang et al.
patent: 6445245 (2002-09-01), Schultz et al.
patent: 6448813 (2002-09-01), Garlepp et al.
patent: 6466063 (2002-10-01), Chen
patent: 6489837 (2002-12-01), Schultz et al.
patent: 6586964 (2003-07-01), Kent et al.
patent: 6590413 (2003-07-01), Yang
patent: 6603329 (2003-08-01), Wang et al.
patent: 6639397 (2003-10-01), Roth et al.
patent: 6642741 (2003-11-01), Metz et al.
patent: 6747475 (2004-06-01), Yuffe et al.
patent: 20020010853 (2002-01-01), Trimberger et al.
patent: 20020060602 (2002-05-01), Ghia et al.
patent: 20020101278 (2002-08-01), Schultz et al.
patent: 20030062922 (2003-04-01), Douglass et al.
patent: 20040008054 (2004-01-01), Lesea et al.
Altera, Apex 20K “Programmable Logic Device Family,” Altera Corporation, Ver. 1.1, May 2001.
Altera, Apex II “Programmable Logic Device Family,” Altera Corporation, Ver. 1.1, May 2001.
Bendak, M. et al. (1996). “CMOS VLSI Implementation of Gigabyte/second computer network links,” Dept. of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093-0407, IEEEInternational Symposium on Circuits and Systemspp. 269-272.
Boni, A. et al. (2001). “LVDS I/O Interface for GB/s-per-Pin Operation in 0.35-um CMOS,” IEEE Journal of Solid-State Circuits, 36(4):706-711.
Esch and Manley, Theory and Design of CMOS HSTL I/O Pads, The Hewlett Packard Journal, Aug. 1998.
Xilinx, “Spartan-3 1.2V FPGA Family: Functional Description,” Xilinx, DS099-2 (v1.2) Jul. 11, 2003.
Xilinx, “Virtex-II 1.5V Field Programmable Gate Arrays,” Xilinx, DSO3102 (v1.5), Apr. 2, 2001.
Xilinx, “Virtex-II Platform FPGAs: Detailed Description,” Xilinx, DS031-2 (v3.1) Oct. 14, 2003.
Xilinx, “Virtex-II Pro Platform FPGAs: Functional Description,” Xilinx, DS083-2 (v2.9) Oct. 14, 2003.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Dynamically adjustable termination impedance control techniques does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamically adjustable termination impedance control techniques, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamically adjustable termination impedance control techniques will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3388493

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.