Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
1999-10-28
2004-01-13
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S173000, C711S147000, C710S056000
Reexamination Certificate
active
06678813
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a buffer architecture, and more specifically to a buffer architecture with multiple buffers allocated storage within a common storage area where the allocation is reconfigurable.
2. Description of the Related Art
Buffers are used within systems to provide temporary storage for data. Buffers are either FIFO (First-In-First-Out) or LIFO (Last-In-First-Out). In a FIFO buffer, data is written to the front end of the buffer and is read from the back end of the buffer. In a LIFO buffer, data is written and read from the front end of the buffer. Data in a FIFO buffer “marches” through the buffer and is read in the strict ordering in which it was written. Data in a LIFO buffer is stacked on the buffer and the most recently written data is read before less recently written data.
FIFO buffers are generally implemented as a circular queue having a read pointer which points to the “next” location in the buffer storage to be read and a write pointer which points to the “next” location to be written. The write pointer is used by the control logic of the buffer to access a location where data is to be written in the buffer storage and the read pointer used by the control logic of the buffer to access a location whose data is to be read from buffer storage. A device which is connected to the buffer sends data to the buffer and the control logic writes the data to the buffer storage location corresponding to the write pointer. A device which reads from the buffer reads data presented to it by the control logic which reads the data from the buffer storage location corresponding to the read pointer.
LIFO buffers are generally implemented as a stack with a pointer to the bottom of the stack and a stack pointer to the location in buffer storage where data was last written. The stack pointer is usually both a read pointer and a write pointer. The stack pointer is used by the control logic of the buffer to point to the location in buffer storage where the most recently written data was stored. A device connected to the buffer reads from data presented to it by the control logic which reads the data from the buffer storage location corresponding to the stack pointer, then moves the stack pointer to the location in buffer storage previously written. A device writes data to the buffer and the control logic moves the stack pointer to the next free location in buffer storage and writes the data to the location in buffer storage corresponding to the pointer.
In a conventional buffer mechanism, the size of each buffer storage area is determined in advance and is fixed thereafter, especially in ASIC applications. This fixed allocation can be inefficient and has a larger memory requirement if multiple buffers are required by the system, not all of which will be simultaneously busy or active to the same degree. For example, in a system with two devices or applications needing buffer support, only one of which is active at any time, all of the buffers associated with the inactive device or application may be in an idle state, while the buffers for the active device or application may be of insufficient size for optimal performance.
SUMMARY OF THE INVENTION
Briefly, a system according to one embodiment of the present invention provides a buffer mechanism including at least two buffers, a common storage area coupled to the buffers, and an allocation mechanism coupled to the buffers. The common storage area provides buffer storage for the buffers. The allocation mechanism dynamically reconfigures the common storage area to shift buffer storage allocation between the buffers.
In one embodiment of the present invention, the allocation mechanism can include software routines, circuitry, or a combination of software and circuitry. The allocation mechanism receives an input signal requesting a desired reconfiguration of the common storage area. The allocation mechanism can selectively allocate portions (none, some, or all) of the common storage area to any of the buffers. One advantage of this embodiment of the invention is that it allows an inactive buffer's storage to be completely deallocated and an active buffer to receive the entire common storage area if needed.
Preferably, the allocation mechanism monitors certain parameters and allocates the common storage area responsive to those parameters. The parameters can comprise relative activity of the buffers, the “fullness” of the buffers (based on a comparison of the amount of data written to each buffer but not yet read with the size of the associated buffer storage area), throughput of a system providing the buffers, network traffic of the system, or mass storage activity of the system.
According to another embodiment of the invention, the allocation mechanism marks the boundaries of the regions of the common storage area allocated to each buffer with one or more boundary pointers. A portion of the common storage area allocated to a buffer can be dynamically reconfigured by changing the position of the associated boundary pointer.
To avoid disruption in buffer operation, the allocation mechanism preferably verifies that a requested reconfiguration of the common storage area is valid before performing the requested reconfiguration. The allocation mechanism can reject a requested reconfiguration of the common storage area that is invalid or delay a requested reconfiguration of the common storage area until the requested reconfiguration is valid. A requested reconfiguration of the common storage area can be considered valid if the region of the common storage area to be shifted to a first buffer does not contain data which has been written to a second buffer but not read and the region of the common storage area to be shifted to the first buffer is not adjacent to data which has been written to the first buffer but not read.
According to a further embodiment of the invention, the allocation mechanism produces an output signal. The output signal can indicate success or failure of the requested reconfiguration of the common storage area or that the requested reconfiguration will be delayed.
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Bataille Pierre-Michel
Hewlett--Packard Development Company, L.P.
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