Dynamic word line driver for cache

Details Dynamic word line driver for cache Dynamic word line driver for cache

2000-04-26

2001-04-24

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189070

Reexamination Certificate

active

06222752

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to digital signal processing and more particularly to a memory driver circuit configuration for managing a cache memory device.
BACKGROUND OF THE INVENTION
With the increasing number of applications for computer systems, the demand for computer systems continues to expand. To meet the increasing demand and expanding customer base, computer systems have been provided with ever increasing performance characteristics. The increasing speed of central processing units or CPUs is very apparent. However, to take maximum advantage of the faster CPUs, the other basic computer subsystems must also be constantly improved to be capable of running at the higher system speeds. Moreover, increasing application complexities have also placed greater demands on computer subsystems so that the computer systems not only run at faster speeds but also are capable of handling much more complex applications and data handling requirements.
In computer systems, cache memory subsystems have become a critical area for improvement. More specifically, wordline driver circuits, which control the memory cells in cache arrays, have not undergone many changes. In the past, wordline drivers were simple and straight forward because caches were simple and there were fewer operations implemented in the cache. With more powerful, faster and more complex microprocessors, cache subsystems and wordline driver circuits must also be improved to make optimum use of the increased CPU capabilities. For most applications, the size and speed of the cache circuitry must be improved to allow greater amounts of programming and data to be available for even faster access by the CPU in running modern complex computer applications. As bandwidths increase, however, timing problems may be created, which in some cases may be sufficiently severe to affect the reliability of the circuit. Thus, there is a need for an improved cache subsystem and cache controlling circuitry in order to provide even greater cache capabilities for modern computer system applications.
SUMMARY OF THE INVENTION
A method and apparatus is provided for implementing a cache control system effective to eliminate many of the timing problems occurring in higher bandwidth, dynamic cache control systems. In one exemplary embodiment, a dummy content addressable memory (CAM) cell is provided and is strategically placed on the chip layout farthest away from the cache word line driver circuit. The dummy output signal is a required input to a cache hit evaluation circuit such that premature cache hit outputs are eliminated. The dummy cell is designed to quickly discharge a cache match line and indicate a non-hit status when any address bit line, particularly those farthest away from the word line driver circuit, produces a mismatch indication. The methodology is especially useful in expanded bandwidth, dynamic systems where bandwidths are more extensive and the system is synchronized to predetermined and fixed duration clock cycles. The cache control system also provides a prefetch mode for determining whether next-cycle addresses are located in the cache. In a refill mode the cache control circuit transfers date into the cache from the L2 cache or the main memory or other memory storage devices. A test mode is included and functions to determine that the cache is not defective. An “I-Cache” block invalidation (ICBI) mode is implemented to perform a prefetch operation and if a “valid” bit is low, it means that that the cache line or word line becomes invalid and is not used. The cache also may generate a reset signal which means that the data in the cache is invalid. When the reset signal is generated, the system CPU will not use the data.


REFERENCES:
patent: 5299147 (1994-03-01), Holst
patent: 5640339 (1997-06-01), Davis et al.
patent: 5715188 (1998-02-01), Covino et al.
patent: 6118682 (2000-09-01), Martin

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