Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1998-02-17
2000-09-19
Yoo, Do Hyun
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711202, 711203, G06F 1200
Patent
active
061227102
ABSTRACT:
A method and apparatus is provided for implementing a cache control system effective to eliminate many of the timing problems occurring in dynamic, high bandwidth cache control systems. In one exemplary embodiment, a dummy content addressable memory (CAM) cell is provided and is strategically placed on the chip layout farthest away from the cache word line driver circuit. The dummy output signal is a required input to a cache hit evaluation circuit such that premature cache hit outputs are eliminated. The dummy cell is designed to quickly discharge a cache match line and indicate a non-hit status when any address bit line produces a mismatch indication, especially for expanded bandwidth and dynamic systems where the address lines are more extensive and the system is synchronized to predetermined clock cycles. The cache system further operates in a prefetch mode to determine hits for next in-line requested addresses. The system further includes implementations for test mode, refill, ICACHE block invalidation and cache reset signal generation.
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Kumar Manoj
Pham Huy Van
England Anthony V. S.
International Business Machines - Corporation
Moazzami Nasser
Wilder Robert V.
Yoo Do Hyun
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