Dynamic type semiconductor memory device with a refresh function

Details Dynamic type semiconductor memory device with a refresh function Dynamic type semiconductor memory device with a refresh function

1991-08-27

1993-10-05

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Data refresh

36523003, 36523002, 365193, 365229, G11C 700

Patent

active

052511766

ABSTRACT:
A dynamic type semiconductor memory device includes m memory blocks each having a plurality of memory cells, and a plurality of sense amplifier groups associated with the respective memory blocks. Each sense amplifier group senses and amplifies data of a selected memory cell in the related memory block. The memory device further includes a circuit for generating a refresh instruction detecting signal in response to an externally applied refresh mode indicating signal, and circuitry responsive to a block designating signal and the refresh instruction detecting signal for activating each of the sense amplifier groups in such a manner that only start timings for the sensing operations of the sense amplifier groups related to the designated memory blocks may differ from each other. This activation circuitry activates the respective sense amplifier groups related to the memory blocks designated by the block designating signal in such a manner that their sensing operations may have the same start timing in the normal mode. This device significantly reduces current dissipation in the refresh mode, while the access time in the normal mode is not adversely affected. This device is suitable for use as an internal memory of a battery back-up type computer because of its small load on the battery.

REFERENCES:
patent: 4222112 (1980-09-01), Clemons et al.
patent: 4796232 (1989-01-01), House
patent: 4933907 (1990-06-01), Kumanoya et al.
patent: 4934826 (1990-06-01), Miyatake et al.
"Synchronous Memory Refresh Scheme Which Supports Several Refresh Rates Without Jumpers on Cards or Planars", IBM Technical Disclosure Bulletin, vol. 32, No. 88, Jan. 1990.
"A 64K Bit MOS Dynamic Ram with Auto/Self Refresh Functions", by Yamada et al, Institute of Electronics and Communication Engineers, Transactions (C), vol. 10-66C, No. 1, Jan. 1983, pp. 62-69.

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