Dynamic-type semiconductor memory device operable in test mode a

Details Dynamic-type semiconductor memory device operable in test mode a Dynamic-type semiconductor memory device operable in test mode a

1991-07-30

1993-05-04

Dixon, Joseph L.

Static information storage and retrieval

Read/write circuit

Testing

365 63, 371 211, 371 212, G11C 506, G11C 2900

Patent

active

052087786

ABSTRACT:
A dynamic-type semiconductor memory device has a test mode of simultaneously carrying out functional testing on a plurality of bits of memory cells. In data writing in the test mode, data inverted from the write-in data is written in at least a 1-bit memory cell out of the plurality of bits of memory cells selected simultaneously, and the same data as the write-in data is written in the remaining memory cells. In data reading in the test mode, the data of those of the memory cells selected simultaneously, in which the inverted data is written are inverted and read, while the data of the remaining memory cells are read as they are. Logic processing is carried out on the read-out data of the plurality of bits, so that a logic value indicating acceptability of the semiconductor memory device is output, depending on a result of determination as to whether or not the read-out data is the same as each other.

REFERENCES:
patent: 4692900 (1987-09-01), Ooami et al.
patent: 4866676 (1989-09-01), Crisp et al.
Masaki Kumanoya et al., "A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode", IEEE Journal of Solid State Circuits, vol. SC20. No. 5, Oct. 1985, pp. 909-913.
Koichiro Mashiko et al., "A 90ns 4Mb DRAM in a 300 mil DIP", IEEE International Solid State Circuits Conference 1987, pp. 12-13.

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