Dynamic type semiconductor memory device operable in a self-refr

Details Dynamic type semiconductor memory device operable in a self-refr Dynamic type semiconductor memory device operable in a self-refr

1993-03-30

1995-04-04

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Data refresh

365193, 365194, 365195, G11C 700

Patent

active

054043352

ABSTRACT:
A dynamic type semiconductor memory device includes a CBR detecting circuit for detecting a timing condition of /CAS before /RAS, an RS flip-flop which is set depending on an output of the CBR detecting circuit, a pulse generating circuit which is activated in response to an output of the RS flip-flop and generates a one-shot pulse in response to the fall of the external row address strobe signal /RAS, a delay circuit which delays an output of the pulse generating circuit by a predetermined time period, an RS flip-flop which is set by an output of the delay circuit and is reset by the row address strobe signal /RAS, and a NOR circuit which receives outputs of the RS flip-flops, the row address strobe signal /RAS and the column address strobe signal /CAS and generates an internal CAS signal .phi.CAS. In the dynamic type semiconductor memory device, which has a function of checking a refreshing counter for generating a refresh address and is operable in a self-refreshing mode, restriction on a timing condition of an external column address strobe signal /CAS is mitigated in the self-refreshing operation.

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