Dynamic-type semiconductor memory device

Details Dynamic-type semiconductor memory device Dynamic-type semiconductor memory device

1998-12-02

2003-02-18

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000, C257S303000, C257S305000

Reexamination Certificate

active

06521938

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a dynamic type semiconductor memory device (DRAM) having memory cells each having a trench capacitor structure.
In general, a DRAM includes memory cells each of which comprises one MOS transistor and one capacitor. A trench capacitor structure is well known as the structure of such a memory cell.
FIG. 1
is a cross-sectional view of a memory cell having a conventional substrate-plate type trench structure, the view being taken along a line extending in a direction in which bit lines extend.
The memory cell shown in
FIG. 1
comprises a MOS transistor
200
and a capacitor
300
. A semiconductor substrate
100
has an n-type well
101
, on which a p-type well
102
is formed. The p-type well
102
is divided into island-shaped element regions by insulating films
103
. The MOS transistor
200
comprises a gate electrode
202
and n
+
-type source and drain diffusion layers
203
and
204
. The gate electrode
202
is formed on the p-type well
102
, with a gate insulating film
201
interposed between the gate electrode
202
and the p-type well
102
. The n
+
-type source and drain diffusion layers
203
and
204
are self-aligned with the gate electrode
202
. The gate electrode
202
is formed of a laminated film consisting of, e.g., a polysilicon film
202
a
and a Wsi film
202
b
. A plurality of gate electrodes having such a structure are arranged in rows, and thus included in word lines thereof.
The capacitor
300
is provided in a groove
301
. A capacitor insulating film
302
is formed on the inner wall of the groove
301
, and further a storage electrode
303
is filled in the inner remaining region of the groove
301
. The n-type well
101
is used as a plate electrode of the capacitor. An insulting film
304
is formed on the outer wall of an upper portion of the groove
301
.
The storage electrode
303
filled in the groove
301
is connected to the source diffusion layer
203
of the MOS transistor
200
which is diffusely formed to be partially stacked on the storage electrode
303
. A bit line
400
is connected to the drain diffusion layer
204
, and extends to in a direction perpendicular to the word line.
In the above memory cell structure, each of the word lines has portions functioning as gate electrodes and portions not functioning as gate electrodes. The latter portions are located above capacitor regions of memory cells arranged adjacent to each other in a direction in which said each word line extends.
In such a manner, in the memory cell having the conventional trench capacitor structure, the storage electrode
303
is filled in the capacitor groove
301
, thus increasing the total area of the outer peripheral surfaces of the capacitor
300
which is provided, with the capacitor insulating film
302
interposed between the storage electrode
303
and the n-type well
101
. By virtue of this structure, memory cells can be formed smaller and a DRAM can be formed at a higher integration density.
Furthermore, in the conventional memory cell, the area of the opening of the capacitor groove is reduced as the memory cell area is reduced. Hence, the depth of the capacitor groove needs to be increased to secure a sufficient capacitance.
In general, it is difficult to form a groove having a great aspect ratio. In order to restrict the increase in the aspect ratio, and secure a sufficient capacitance, it is considered to use an insulating film having a high dielectric constant, e.g., a high dielectric constant material film as a capacitor insulating film. However, in the conventional memory cell structure, the high dielectric constant material film can hardly be used as the capacitor insulating film since the source and drain diffusion layers of a MOS transistor are formed after a capacitor is formed to be filled in the substrate. To be more specific, in general, when a high dielectric constant material film is subjected to a heating step using heat of approximately 800° C., it changes in composition, etc. and its dielectric constant lowers, increasing leakage current. Therefore, if it is used as the capacitor insulating film in the conventional memory structure, when the source and drain diffusion layers are subjected to a heating step, as impurity activation, the function of the capacitor lowers.
In addition, there is a possibility that the composition of the film may change such that for example, oxygen removes from the high dielectric constant material film, or the high dielectric constant material film may react with the semiconductor substrate or the storage electrode. Furthermore, in the conventional trench capacitor structure, the gate electrodes
202
of the MOS transistors are arranged in rows, and included in the word lines. They, as shown in
FIG. 2
(cross-sectional view), extend from positions above element regions to positions above the outsides thereof, and thus floating capacitors (represented by C in
FIG. 2
) generate between the gate electrodes and bulk regions of the MOS transistors. The floating capacitor causes a signal delay at the word line, as a result of which the memory cell cannot operate at a high speed.
BRIEF SUMMARY OF THE INVENTION
In view of the foregoing, the object of the present invention is to provide a dynamic type semiconductor memory device and a manufacturing method for the same, wherein gate electrodes are provided only above element regions, thus achieving a trench capacitance structure wherein the floating capacitance is smaller and each memory cell can operate a higher speed.
According to the present invention, a dynamic type semiconductor memory device is provided, which comprises:
a semiconductor substrate;
element regions formed on the semiconductor substrate such that the element regions are island-shaped and isolated from each other;
MOS transistors including gate electrodes and source and drain diffusion layers, and arranged in rows in a first direction and also arranged in rows in a second direction perpendicular to the first direction, the gate electrodes being located above the element regions, the source and drain diffusion layers self-aligned with the gate electrodes;
capacitor grooves formed in the semiconductor substrate and located at end portions of the element regions;
capacitors including capacitor insulating films and storage electrodes, the capacitor insulating film being constituted by high dielectric constant materials formed on inner walls of the capacitor grooves, the storage electrodes being formed within the capacitor grooves;
connection conductors each connecting the storage electrode of a respective one of the capacitors and one of the source and drain diffusion layers of a respective one of the MOS transistors;
word lines arranged such that each of the word lines connect the gate electrodes of those of MOS transistors which are arranged in an associated one of the rows in the first direction; and
bit lines arranged such that each of the bit lines connects the others of the source and drain diffusion layers of those of the MOS transistors which are arranged in an associated one of the rows in the second direction.
In the dynamic type semiconductor memory device, it is preferable that the word lines be formed of conductive films constituting layers differing from layers constituted by the gate electrodes.
In the dynamic type semiconductor memory device, it is preferable that the word lines be formed of conductive films constituting layers located above layers constituted by the gate electrodes.
In the dynamic type semiconductor memory device, it is preferable that the gate electrodes of the MOS transistors have substantially the same widths as the element regions.
In the dynamic type semiconductor memory device, it is preferable that:
the capacitors further include plate electrodes formed on the inner walls of the capacitor grooves and containing strontium ruthenium oxides;
the capacitor insulating films be formed of barium strontium titanium oxide, and provided on surfaces of the plate electrodes; and
the storage electr

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