Dynamic type memory device including a reference potential gener

Details Dynamic type memory device including a reference potential gener Dynamic type memory device including a reference potential gener

1986-01-31

1988-11-29

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Complementing/balancing

365189, 365150, G11C 700, G11C 1124

Patent

active

047886684

ABSTRACT:
A dynamic type memory device includes a plurality of one-transistor/one-capacitor type memory cells which are arranged in a matrix, first bit lines connected to the memory cells, second bit lines, and first capacitors respectively connected to the second bit lines and having a capacitance equal to 1/2 of that of the memory cell capacitor. This memory device further has second capacitors respectively connected to the second bit lines and having a capacitance equal to 1/2 of that of the memory cell capacitor, first switching transistors connected respectively between a power source terminal and the first capacitors, and second switching transistors connected respectively between a ground terminal and the second capacitors.

REFERENCES:
patent: 4379346 (1983-04-01), Ochii et al.
patent: 4419743 (1983-12-01), Taguchi et al.
patent: 4503523 (1985-03-01), Cavaliere et al.
patent: 4547868 (1985-10-01), Childers et al.
patent: 4578776 (1986-03-01), Takemai et al.
Lu et al., "Half-VDD Bit-Line Sensing Scheme in CMOS DRAM's," IEEE Journal of Solid-State Circuits, vol. SC-19, No. 4, Aug. 1984.
Nakano et al., "A Sub-100 ns 256K DRAM with Open Bit Line Scheme," IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, Oct. 1983.

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