Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2008-07-01
2008-07-01
Cho, James H (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S021000
Reexamination Certificate
active
07394282
ABSTRACT:
A system may include detection of a low signal received from a transmission line, and uncoupling of a termination circuit from the transmission line in response to the detected low signal. In some aspects, a transition of a strobe signal is then detected, and the termination circuit is coupled to the transmission line in response to the detected transition.
REFERENCES:
patent: 5023488 (1991-06-01), Gunning
patent: 5559447 (1996-09-01), Rees
Kudoh, Junya et al., “A CMOS Gate Array with Dynamic-Termination GTL I/O Circuits”, Proceedings of the International Conference on Computer Design: VLSI in computers & Processor (ICCD '95), 1062-6404, © 1995 IEEE, pp. 25-29.
Gerosa Gian
Kontu Amrish
Patel Binta M.
Sinha Manoj K.
Buckley Maschoff & Talwalkar LLC
Cho James H
Intel Corporation
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