Dynamic to static logic translator or pulse catcher

Details Dynamic to static logic translator or pulse catcher Dynamic to static logic translator or pulse catcher

1994-07-28

1995-10-24

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

327206, 327210, H03K 190175, H03K 1902

Patent

active

054613310

ABSTRACT:
A system and method is provided which includes a set of N and P type transistors connected such that both positive active and negative dynamic logic input pulses may be received. The pulse catcher circuit of the present invention then outputs a static logic level based upon the input pulses. A first input circuit is included that receives the data signal and outputs a level (voltage or absence of a voltage) to an output invertor circuit which is used in conjunction with a feedback circuit as a latch to maintain the output at the desired level. The feedback circuit ensures that the level will be maintained in a stable state (i.e. ground potential for a logical "0" and Vdd for a logical "1"). In this manner the static logic levels output from the circuit will be maintained until another dynamic pulse is received. Additionally, the pulse catcher circuit will always provide a consistent static logic output, even when both of the dynamic logic input signals are in their active states.

REFERENCES:
patent: 3493785 (1970-02-01), Rapp
patent: 4506168 (1985-03-01), Uya
patent: 4594519 (1986-06-01), Ohtani et al.
patent: 4607173 (1986-08-01), Knoedl, Jr.
patent: 4616148 (1986-10-01), Ochi et al.
patent: 4728820 (1988-03-01), Lee
patent: 4800300 (1989-01-01), Walters, Jr.
patent: 4808840 (1989-02-01), Chung et al.

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