Dynamic to static converter with noise suppression

Details Dynamic to static converter with noise suppression Dynamic to static converter with noise suppression

2006-01-24

2006-01-24

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S093000, C326S098000

Reexamination Certificate

active

06989691

ABSTRACT:
An apparatus is disclosed which includes a converter circuit and a noise suppression circuit. The converter circuit has a dynamic logic input, and is configured to generate a static logic output on an output node responsive to the dynamic logic input. The noise suppression circuit is coupled to receive a clock signal and is coupled to the output node. Responsive to a first phase of the clock signal, a precharge of a dynamic logic circuit generating the dynamic logic input occurs. The noise suppression circuit is configured to actively drive the static logic output on the output node responsive to the first phase. In some embodiments, the noise suppression circuit may reduce the noise sensitivity of the static logic output during the precharge phase, and may not impede operation of the converter circuit during the evaluate phase.

REFERENCES:
patent: 5841304 (1998-11-01), Tam
patent: 5892372 (1999-04-01), Ciraula et al.
patent: 5917355 (1999-06-01), Klass
patent: 6531897 (2003-03-01), Milshtein et al.
patent: 2003/0062925 (2003-04-01), Nedovic et al.

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