Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2002-04-15
2004-04-06
Tran, Anh (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S098000, C326S093000
Reexamination Certificate
active
06717442
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the field of dynamic and static logic circuits, and more particularly to noise issues in dynamic to static conversion.
2. Description of the Related Art
Dynamic logic circuits are a circuit design tool often used in integrated circuits. Generally, dynamic logic circuits are precharged to a first state and then conditionally discharged to a second state according to one or more inputs. In contrast, static logic circuits continuously respond to inputs by driving the outputs to high or low states according to the state of the inputs. Since the inputs of dynamic logic circuits are only connected to the discharge transistors (as opposed to static logic circuitry in which a given input is typically connected to at least two transistors, one which may charge the output and one which may discharge the output), the capacitive load on the inputs may be comparatively lower than equivalent static logic circuitry. Additionally, the use of only discharge transistors may inherently speed the evaluation of the logic circuitry. Thus, dynamic logic circuitry may typically evaluate more rapidly than the corresponding static logic circuitry.
One complication introduced with the use of dynamic logic circuits is the need to convert the dynamic logic signals produced by the dynamic logic circuits to static logic signals when the dynamic logic signals are input to static circuitry, dynamic circuitry operating on a different phase of the clock, etc. In particular, the conversion hides the precharge of the dynamic circuitry during the precharge phase from the static circuitry, providing a steady value during the precharge phase equal to the result of the evaluate phase. In this fashion, the static logic circuitry does not reevaluate based on the precharge values.
Typically, the circuit shown in
FIG. 1
may be used to convert dynamic logic signals to static logic signals. The circuit includes a dynamic logic circuit comprising a precharge transistor
10
, one or more pulldown transistors
12
(shown in block form), and an evaluate transistor
14
. The precharge transistor
10
is activated by the clock signal coupled to its gate node and precharges the node
16
during the precharge phase (clock low in this example). The dynamic inputs of the dynamic logic circuit are coupled to the pulldown transistors
12
, which conditionally discharge the node
16
during the evaluate phase (clock high in this example). The evaluate phase is controlled by the evaluate transistor
14
, which has its gate node coupled to the clock signal as well.
The node
16
is connected to the gate node of the transistors
18
and
20
, which are coupled to the output node of the circuit. During the evaluate phase (when the transistor
22
is active), the transistors
18
and
20
function as an inverter, inverting the value on the node
16
to provide the output. During the precharge phase (clock low), the transistor
22
is deactivated. The precharge of the node
16
activates the transistor
20
and deactivates the transistor
18
. Since both the transistor
18
and the transistor
22
are deactivated, the precharge does not pass to the output node. Thus, the output node remains at the value generated during the evaluate phase of the dynamic logic circuit.
To prevent the output node from floating during the precharge phase, the cross coupled inverters
24
and
26
are provided to latch the output value. So as not to impact the transition speed of the output node in response to the dynamic circuit operation during the evaluate phase, the inverter
24
is made relatively weak as compared to the other transistors in the circuit. Since the inverter
24
is the only circuitry supplying the value on the output node during the precharge phase and the inverter
24
is weak, the circuit shown in
FIG. 1
is noise sensitive. That is, noise injected on the output node (typically the capacitive “crosstalk” from other wires near the wires connected to the output node) may have the tendency to flip the state of the output node, thus causing erroneous operation.
Typically, circuit designers attempt to limit the noise injected on the output node by limiting the distance that the wires attached to the output node travel (thus limiting the injection of noise by limiting the number and length of nearby wires) or by shielding the wires. Limiting the routing distance complicates the design and limits the use of the circuit shown in FIG.
1
. Adding shielding increases the impact of the circuit shown in
FIG. 1
on the wireability of the integrated circuit and may create additional layout complexities for the integrated circuit.
SUMMARY OF THE INVENTION
An apparatus is disclosed which includes a converter circuit and a noise suppression circuit. The converter circuit has a dynamic logic input, and is configured to generate a static logic output on an output node responsive to the dynamic logic input. The noise suppression circuit is coupled to receive a clock signal and is coupled to the output node. Responsive to a first phase of the clock signal, a precharge of a dynamic logic circuit generating the dynamic logic input occurs. The noise suppression circuit is configured to actively drive the static logic output on the output node responsive to the first phase. In some embodiments, the noise suppression circuit may reduce the noise sensitivity of the static logic output during the precharge phase, and may not impede operation of the converter circuit during the evaluate phase.
The noise suppression circuit, in one embodiment, includes at least a first transistor and a second transistor. The first transistor has a first node, a second node, and a first control node. The first node is coupled to a power supply and the first control node is coupled to receive a feedback signal corresponding to the static logic output. The second transistor has a third node connected to the second node, a fourth node connected to the output node, and a second control node controlled by the clock signal. The second transistor activates during the first phase responsive to the clock signal.
A method is also contemplated. A static logic output is generated on a node responsive to a dynamic logic input. The static logic output is actively driven on the node responsive to a first phase of a clock signal, wherein a precharge of a dynamic logic circuit generating the dynamic logic input occurs responsive to a first phase of the clock signal.
REFERENCES:
patent: 5841304 (1998-11-01), Tam
patent: 5892372 (1999-04-01), Ciraula et al.
patent: 5917355 (1999-06-01), Klass
US 2003/0062925 A1, Nedovic et al, Method and System for improving Speed in a Flip-Flop, Patent Application Publicatio.
BroadCom Corporation
Merkel Lawrence J.
Tran Anh
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