Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-07-27
2004-09-07
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S345000, C257S376000, C257S402000, C257S040000, C257S404000, C257S364000, C257S904000, C257S903000, C327S322000, C327S534000, C327S537000, C438S149000, C438S282000, C438S289000, C438S217000
Reexamination Certificate
active
06787850
ABSTRACT:
TECHNICAL FIELD
This invention concerns a dynamic threshold voltage MOS transistor (insulated gate Transistor) fitted with an integrated current limiter. This device is intended in particular to be made on an SOI (silicon on insulator) type substrate, in other words a substrate having a thin surface layer of silicon insulated by an underlying layer of oxide.
The invention also concerns a process for making such a device in a particularly compact form with a view to integrating it into a circuit.
The invention finds applications particularly in the manufacture of CMOS circuits operating with very low supply voltages such as for example micro-processors or digital signal processors (DSP).
PRIOR ART
The prior art is shown particularly in documents (
1
), (
2
), (
3
) and (
4
) mentioned below and the references for which are given at the end of this description.
A usual MOS transistor may be considered as being made up of two intrinsic components. The first component is the MOS transistor itself, in which the current, controlled by the gate, flows between the drain and the source, and in which the substrate is subject to fixed polarisation. The second component is a bipolar parasitic transistor for which the drain and the source act as transmitter and collector, and the substrate acts as the base.
Document (
1
) proposes the simultaneous activation of the MOS component and the bipolar component so as to increase the total current supplied by the device, and to do this by connecting the transistor gate to its substrate. Such a device is however little used on account of the significant increase in static current related to the operation of the bipolar component. Indeed, minimal static current is generally required in CMOS circuits.
Document (
2
) proposes a hybrid mode of operation of the MOS and shows that, by means of the connection between the gate and the substrate, the threshold voltage of the MOS may be lowered and the transistor characteristic gradient under the threshold may be improved at low voltage, in other words before the bipolar transistor is activated. This operational principle has given rise to the dynamic threshold voltage transistor described in document (
3
) “Dynamic Threshold Voltage MOSFET” or “DTMOS”.
The symbolic electrical diagram of a dynamic threshold voltage MOS transistor (DTMOS) is shown in the appended FIG.
1
.
The transistor
10
comprises, like any MOS transistor, a drain terminal
12
, connected to a source terminal
14
by a channel, and a gate terminal
16
to control the current passing through the channel.
Moreover, an electrical connection
18
is established between the gate and the substrate. In the figure a substrate contact terminal to which the electrical connection
18
is connected is identified with the reference
11
.
The threshold voltage V
t
of a MOS transistor depends on the voltage applied on its substrate.
As shown in document (
4
), the voltage V
t
may be expressed by the following relation.
V
t
=V
fb
+2&phgr;
f
+&ggr;{square root over (2&phgr;
f
−V
bs
)}
In this expression, V
fb
is the flat band voltage, &phgr;
f
is the Fermi potential, &ggr; is the substrate effect coefficient and V
bs
is the potential difference applied between the substrate and the transistor source.
When the gate is connected to the substrate as is the case for the DTMOS, the voltage applied to the gate is also applied to the substrate. The threshold voltage is then dependent on the voltage applied to the gate, which justifies the term “dynamic threshold voltage transistor”.
During normal operation, in respect of an NMOS transistor, taken here by way of illustration, the polarisation applied to the gate is positive relative to the source. It brings about the forward bias of the junction existing between substrate and source, and possibly the forward bias of the junction between substrate and drain (depending on the polarisation applied to the drain). If high voltage is applied to the gate, the same voltage applied to the substrate causes a significant current to pass in the junction. This contributes to the increase in total static current in a circuit fitted with the DTMOS component.
The maximum acceptable current for a DTMOS in SOI technology is about 0.6 V, so as to limit this junction current to approximately 100 pA per micrometer of transistor width. Using a DTMOS at a higher supply voltage requires a device to be inserted which enables the junction current to be reduced. Such a device is inserted between the gate and the substrate and is called a current limiter. Reference may be made on this subject to document (
3
).
The current limiter is a second MOS transistor for which different configurations of polarisation are conceivable.
A first proposed configuration is shown in the appended FIG.
2
.
FIG. 2
shows the MOS transistor
10
of
FIG. 1
, which is fitted with a current limiter in the form of a second MOS transistor
20
inserted between the gate terminal
16
and the substrate terminal
11
.
The gate
26
of the second transistor is polarised at the supply voltage in the case of an NMOS transistor and is polarised at the earth in the case of a PMOS transistor.
Another possible polarisation configuration of the second transistor is shown in the appended FIG.
3
.
It is distinguished from the configuration in
FIG. 2
essentially in that the gate
26
of the second transistor
20
is henceforth connected to its source.
It should be specified that the second transistor
20
is a conventional transistor providing no access to the substrate. Its substrate is floating.
One essential difficulty related to the manufacture of a device according to the diagrams in
FIG. 2
or
3
lies in the fact that making the limiter transistor and the connections with the first transistor is incompatible with the requirements for reducing the sizes of components.
Indeed, the search for an ever greater integration density of components does not allow the electrical diagram of the devices mentioned above to be transcribed directly in an integrated version.
DISCLOSURE OF THE INVENTION
The purpose of the present invention is to propose a DTMOS transistor device with current limiter, which. does not have the difficulties above and is able to be made in the form of an integrated circuit.
A particular purpose is to propose a device of this type which allows the number and range of connections required between the transistors to be reduced, so as to allow it to be made compactly.
Another purpose is propose a particularly cost-effective process for manufacturing the device.
To fulfil these purposes, a more precise object of the invention is a semi-conductor device, comprising on a substrate:
a first dynamic threshold voltage MOS transistor with a gate, and a channel of a first conductivity type, and
a current limiter means connected between the gate and the channel of said first MOS transistor.
In accordance with the invention, the first MOS transistor is fitted with a first doped zone of the first conductivity type, connected to the channel, and the current limiter means comprises a second doped zone of a second conductivity type, placed against the first doped zone and electrically connected to the first doped zone by an ohmic connection path.
In terms of the invention, the ohmic connection between the first and second doped zones of a simple connection is distinguished by physical contact resulting from the juxtaposition of these areas.
The ohmic connection may be made, for example, by a layer of electrically conductive material, such as a layer of silicide, which connects the first and second doped zones to each other.
In a particular embodiment of the device of the invention, the current limiter means may be a second MOS transistor. In this case, the second doped zone and a third doped zone of the same conductivity type as the second doped zone may form the source and drain of said transistor.
Between the source and drain of the second transistor, in other words between the second and third doped zones, is a channel area of an opposite c
Commissariat a l'Energie Atomique
Ortiz Edgardo
Thelen Reid & Priest LLP
Wilson Allan R.
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