Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-30
2002-10-15
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S353000, C257S642000, C257S901000
Reexamination Certificate
active
06465823
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-186995, filed Jun. 30, 1999; and No. 2000-175512, filed Jun. 12, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which a well under the channel of a MISFET is electrically connected to a gate electrode, and a method of manufacturing the same.
Conventionally, to reduce power consumption of a semiconductor device, a power supply voltage V
dd
is continuously dropped. However, a threshold voltage V
th
of a MISFET is not so largely dropped in order to prevent any increase in OFF-current. Hence, a driving capability (drain current) I
d
of a transistor tends to be low.
As a device for solving this problem, a DTMISFET (Dynamic Threshold Voltage Metal insulator Semiconductor Field Effect Transistor) has been proposed (Fariborz Assaderaghi, et al, “Dynamic threshold-voltage MOSFET (DTMOS) for Ultra-Low voltage VLSI”, IEEE Trans. Electron Devices, Vol. 44, pp. 414-421, 1997).
The structure of a DTMISFET (DTMOSFET) will be described with reference to
FIGS. 26A and 26B
.
FIG. 26A
is a perspective view showing the structure of a conventional DTMISFET.
FIG. 26B
is a cross-sectional view showing a section taken along a line V-V′ in FIG.
26
A. Referring to
FIGS. 26A and 26B
, reference numeral
3500
denotes an SOI substrate;
3501
, an Si substrate;
3502
, an insulating layer;
3503
, an Si-body (well region);
3504
, an n+-type source and drain;
3505
, a gate insulating film;
3506
, a gate electrode made of polysilicon; and
3507
, a p+type diffusion layer serving as a contact to a metal plug
3508
connected to the gate electrode.
A DTMISFET is a MISFET in which the gate electrode and the well (Si-body) under the channel are electrically connected and has an advantage that although a power supply voltage V
dd
is low, the driving capability is large, and the OFF current is small. The reason for this advantage is explained by the principle of operation in which the gate voltage is transmitted to the substrate to generate the substrate bias effect, so a threshold voltage V
th
is low in the transistor ON state and high in the OFF state.
The device also has the following advantages.
(1) One of reasons why the DTMISFET can realize a high driving capability is that the vertical electric field perpendicular to the channel plane is small, and carrier mobility is large.
(2) The S-factor always has an ideal value of approximately 60 mV/decade (best value at room temperature) in a region where no short channel effect occurs.
(3) A low threshold voltage V
th
that is suggested to be unrealizable by a MISFET using a metal gate electrode (e.g., gate using TiN) with a midgap work function can be realized.
However, a DTMISFET has the following disadvantages and therefore is not put into practical use for a long time.
(1) To form the contact area (contact hole and metal plug) connecting between polysilicon gate electrode and the Si-body, the device occupation area increases to result in complex manufacturing process. As shown in
FIG. 27
, when two contacts for connecting the gate and well region are formed for one transistor, the device occupation area. increases. Contact holes are formed on both the left and right sides of the Si-body
3502
to reduce the resistance in the Si-body portion. The same reference numerals as in
FIGS. 26A and 26B
denote the same parts in
FIG. 27
, and a detailed description thereof will be omitted.
(2) The high body resistance causes RC delay in the gate wiring, which readily adversely affects the circuit operation.
(3) The source/drain junction capacitance is larger than that of a conventional MOSFET.
(4) A forward bias applied to the p-n junction between the source/drain and the Si-body, and when the power supply voltage V
dd
exceeds about 0.7 V, the leakage current increases to make the device unusable.
In recent years, to reduce the p-n junction leakage between a source/drain and an Si-body, an attempt of connecting a gate and body via a capacitor has been proposed (IEEE International Solid-State Circuits Conference Digest of Technical Papers, p. 292, 1997). However, an increase in device area due to capacitor formation poses a serious problem (as described in the above reference, a p-n junction diode also need to be formed when we connect a gate and body via a capacitor).
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device capable of reducing the occupation area of a DTMISFET and simplifying the manufacturing process, and a method of manufacturing the same.
In order to achieve the above object, the present invention has the following arrangements.
According to the present invention, there is provided a semiconductor device formed on a semiconductor substrate in which a gate electrode of a MISFET is electrically connected to a well region under a channel of the MISFET, wherein the MISFET is formed in an island-shaped element region formed on the semiconductor substrate, and electrical connection between the gate electrode of the MISFET and the well region are electrically connected via a sides of the island-shaped element.
According to the present invention, there is provided a semiconductor device in which a semiconductor substrate including an island-shaped element region comprised of a lower structure and an upper structure formed on the lower structure and having a smaller cross-sectional area parallel to a surface of the substrate than that of the lower structure; a gate insulating film formed on an upper surface of the upper structure of the element region; a sidewall insulating film formed on an upper surface of the lower structure and along a side surface of the upper structure of the element region; and a gate electrode connected to an upper surface of the gate insulating film, an upper surface of the sidewall insulating film, and a side surface of the lower structure of the element region.
According to the present invention, there is provided a semiconductor device in which a semiconductor substrate including an island-shaped element region composed of a lower structure and an upper structure formed on the lower structure and having a smaller cross-sectional area parallel to a surface of the substrate than that of the lower structure; a gate insulating film formed on an upper surface of the upper structure of the element region; a gate electrode formed on the gate insulating film; an element sidewall insulating film formed along a side of the upper structure of the element region and a side of the gate electrode that have an upper surface lower than an upper surface of the gate electrode; and a contact electrode formed on a side of the lower structure of the element region and a side of the sidewall insulating film and electrically connected to the gate electrode and the side of lower structure of the element region.
According to the present invention, there is provided a semiconductor device in which a semiconductor substrate including an island-shaped element region comprised of a lower structure and an upper structure formed on the lower structure and having a smaller cross-sectional area parallel to a surface of the substrate than that of the lower structure; a gate insulating film formed on an upper surface of the upper structure of the element region; a sidewall insulating film formed on a side of the upper structure of the element region; a capacitor insulating film formed on each of opposite sides of the lower structure of the element region; a gate electrode formed on the gate insulating film; and a capacitor electrode formed on the capacitor insulating film and electrically connected to the gate electrode.
According to the present invention, there is provided a semiconductor device formed on a semiconductor substrate in which a gate electrode of a MISFET is electrically connected to a well region under
Iinuma Toshihiko
Saito Tomohiro
Yagishita Atsushi
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Fourson George
Pham Thanh V
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