Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Thinning of semiconductor substrate
Reexamination Certificate
1999-02-26
2002-03-26
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Thinning of semiconductor substrate
C438S197000, C438S455000, C257S728000
Reexamination Certificate
active
06362078
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the field of semiconductor devices fabrication. More specifically, the present invention relates to fabrication of dynamic threshold voltage devices (DTVD).
(2) Background Information
Dynamic threshold voltage devices (DTVD), include Metal Oxide Semiconductor Field Effect Transistors (MOSFET) configured to obtain higher drain-to-source currents for a same gate voltage. A DTVD is based on a MOSFET that has its body (substrate) debiased (charged).
FIG. 1
schematically illustrates a cross-sectional view through a DTVD
100
. DTVD
100
includes a gate
102
, a source
104
, a drain
106
, the body
108
and a substrate
112
that may be a silicon substrate for example. The body
108
is separated from substrate
112
by an oxide film
110
, as DTVD
100
is built according to Silicon-On-Insulator (SOI) technology. The gate
102
is electrically coupled to body
108
by way of conductor
105
. As the potential applied to the gate raises, body
108
gets charged changing its potential and conducting more current. As the gate voltage increases, the body
108
slowly becomes debiased, such that the threshold voltage V
T
effectively decreases. The increase in the gate voltage and the decrease in the threshold voltage V
T
cause current I
DS
between drain and source, to increase, as I
DS
is proportional to (V
GS
-V
T
)
2
, where V
GS
is the gate-source voltage.
At high frequency, when a signal is applied to a periphery
131
of gate
102
, a certain amount of time &tgr; is required to charge up the gate from periphery
131
of gate
102
to edge
130
thereof. As body
108
is not heavily doped it has a high resistance R. The high resistance R contributes to a high propagation delay RC through the body, where C represents the capacitance of the body. This delay may be an order of magnitude larger than the delay &tgr; to the gate. The DTVD may practically be unusable at very high frequencies, because it takes the body a longer time to charge up than it takes the gate.
REFERENCES:
patent: 5702963 (1997-12-01), Vu et al.
patent: 6191007 (2001-02-01), Matsui et al.
Doyle Brian S.
Liang Chunlin
Roberds Brian E.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Jr. Carl Whitehead
Vockrodt Jeff
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