Dynamic test program generator for VLIW simulation

Details Dynamic test program generator for VLIW simulation Dynamic test program generator for VLIW simulation

2006-08-01

2006-08-01

Beausoliel, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S010000, C714S035000, C714S728000, C714S741000, C703S014000, C703S015000, C716S030000, C716S030000

Reexamination Certificate

active

07085964

ABSTRACT:
A method for functional verification of a design for a parallel processing device includes receiving a sequence of single instructions from a dynamic test program generator, and assembling a plurality of the instructions from the sequence into an instruction word, in accordance with predetermined rules applicable to the parallel processing device. The instruction word is input to a simulator of the parallel processing device so as to determine a response of the device to the instruction word.

REFERENCES:
patent: 6484135 (2002-11-01), Chin et al.
patent: 6606721 (2003-08-01), Gowin, Jr. et al.
patent: 6704859 (2004-03-01), Jacobs et al.

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