Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
1999-09-20
2001-09-25
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000, C326S087000
Reexamination Certificate
active
06294924
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to driver circuits and more particularly to driver circuits for use in information processing systems.
2. Description of the Related Art
In computer and information processing systems, various integrated circuit chips must communicate digitally with each other over common buses. The signal frequency at which this communication occurs can limit the performance of the overall system. Thus, the higher the communication frequency, the better. The maximum frequency at which a system communicates is a function not only of the time that it takes for the electromagnetic wavefronts to propagate on the bus from one chip to another, but also of the time required for the signals to settle to levels that can be reliably recognized at the receiving bus nodes as being HIGH or LOW, referred to as the settling time.
There are several factors which affect the settling time of a signal. For example, the “slew rate” of the launched signal, i.e., the rate at which the voltage level of the launched signal changes from one level to another, is one factor which affects the settling time of the signal. The oscillations in the voltage level of the signal (i.e., the “ringing”) due to the effects of package inductance, pad capacitance and other “parasitics” is another factor which affects the settling time of the signal. Ringing due to reflections from impedance mismatches within the bus system is another factor which affects the settling time of the signal. The voltage level of the launched signal relative to the overall signal swing (i.e., the difference between high and low voltage levels of the signal) is another factor which affects the settling time of the signal. The effectiveness of the termination of the bus is another factor which affects the settling time of the signal.
The operating characteristics of transistors such as CMOS transistors, from which drivers are typically constructed, change under a variety of conditions, often referred to as process, voltage, temperature (PVT) variations. PVT variations may be conceptualized as a box across which the operating characteristics of the transistors move. One of ordinary skill in the art will appreciate that the three characteristics, process, voltage and temperature can be visualized as a three dimensional graph with a “slow corner” identifying a point when the three characteristics affect operating conditions, and a “fast corner” identifying a point when the three characteristics do not greatly affect operating conditions. For example, the operating characteristics may move from a fastest corner of PVT variations to a slowest corner of PVT variations, and everywhere in between. More specifically, the operating characteristics due to PVT variations may change with variations in manufacturing process as well as with variations in operating conditions such as junction temperature and supply voltage levels. The operating characteristics may also change with variations of voltage differences across the transistor terminals of the driver; the voltage differences may change as the voltage level at the output node of the driver changes.
If inadequate compensation is made for these variations, the output slew rate and output impedance of the driver may vary substantially within a particular driver as well as from driver to driver on a chip.
Another characteristic that is desirable to control within a driver is crowbar current. The crowbar current is the current that flows directly between the supply rails of a driver through the pull up and pull down units of a driver if both units are enabled simultaneously. Having high crowbar current may cause the driver to consume more power than necessary to provide adequate driver performance.
It is known to provide drivers having different termination characteristics. For example, a High Speed Transceiver Logic (HSTL) type driver, may be designed to terminate at the driver end of a transmission line; a Dynamic Termination Logic (DTL) type driver may be designed to terminate at the receiver end of a transmission line. Each of these driver types has characteristics that affect the driver when a particular type is chosen for a design. What is needed is a driver that provides adequate performance under the different characteristics that affect the driver design.
SUMMARY OF THE INVENTION
A dynamic termination logic driver, one that terminates signals at the receiver end of a transmission line, controls slew rate over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a driver also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance. The driver includes a pull up circuit having an impedance, the pull up circuit including a pull up output circuit and a buffer circuit, the pull up output circuit including a parallel pull up circuit, a pull up output control circuit, and a pull up slew rate control circuit, wherein the parallel pull up circuit and the pull up output control circuit are coupled in parallel. The driver also includes a pull down circuit having an impedance, the pull down circuit including at least one pull down output circuit, the at least one pull down output circuit including at least one pull down slew rate control circuit, a parallel pull down circuit and a pull down output control circuit, wherein the parallel pull down circuit and the pull down output control circuit are coupled in parallel. The driver also includes a plurality of output elements within the pull up circuit and the pull down circuit, wherein the plurality of output elements are selectively enabled and disabled with a controlled slew rate. The selective enabling and disabling is based on an impedance control code.
In one embodiment, the driver also includes a slowing rate circuit coupled to the pull up circuit and coupled to the pull down circuit, the slowing rate circuit reducing amplitudes of transitory voltage spikes in an output of the driver, and the slowing rate circuit includes a parallel combination of a plurality of diode-connected transistors, each of the diode-connected transistors of the plurality of diode-connected transistors being coupled to a transmission gate. The slowing rate circuit incised a plurality of transmission gates, wherein each transmission gate of the plurality of transmission gates ensures that a rate of switching on a plurality of capacitors coupled to the plurality of transmission gates is slowed by a predetermined amount so as to mitigate a charge sharing effect.
In one embodiment, the pull up slew rate control circuit includes a plurality of pass-gate transistors coupled in series with a plurality of transistors, the plurality of pass-gate transistors responding to a control code, wherein the control code selectively enables one or more of the plurality of pass-gate transistors, the enabling of one or more of the plurality of pass-gate transistors increasing the capacitive loading of the pull up circuit to provide slew rate control.
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patent: 5598107 (1
Ang Michael A.
Starr Jonathan E.
Taylor Alexander D.
Vishwanthaiah Sai V.
Kelton Margaret M.
Le Don Pau
Skjerven Morrill & MacPherson LLP
Sun Microsystems Inc.
Tokar Michael
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