Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
1999-12-22
2001-10-09
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S083000, C326S086000, C710S108000, C710S120000
Reexamination Certificate
active
06300789
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to termination of transmission lines in general and more particularly termination of non-symmetric transmission lines.
2. Description of the Prior Art
Termination of a transmission line such as a high speed interconnect or bus is often used to increase performance through reduction or elimination of reflections. To accomplish this, a digitally controlled impedance driver can be used as a parallel termination, for example, by driving a ‘1’ state onto the bus in unidirectional mode. It is also possible use a similar type of termination but turn on both PMOS and NMOS transistors for a center tapped termination (CTT) type scheme also utilizing the digitally controlled impedance of the driver to match the line impedance.
Examples of such digitally controlled impedance are found in U.S. Pat. No. 5,898,321 and in PCT application W O 99/06845, both of which are assigned to the same assignee as the present invention. Thus, for example, in U.S. Pat. No. 5,898,321, there is included, among other things, a compensation unit which provides an impedance control signal to impedance compensation circuit. This circuit uses a combination of logic and PMOS and NMOS transistors in a center tapped termination scheme to adjust the impedance. Typically in the prior art such termination was included only at one end of the transmission line.
An ideal transmission line has an impedance Zo which when terminated with an identical load impedance Z=Zo will have a reflection coefficient of zero and is the best case for high performance interconnects. However, for example, in a multi-load bus, i.e., a bifurcated bus deviates from this ideal since to terminate one load correctly is to leave another unterminated. Often a scheme is used to approximate the point to point scheme. An embodiment of such an arrangement having a balanced topology is shown in
FIG. 1. A
transmission line is driven at one end by a driver
12
through an impedance of approximately Zo. At the other end of transmission line are two short balanced stubs
16
and
18
terminated respectively by impedances
20
and
22
.
In one embodiment the driver
12
is in a processor integrated circuit (commonly called a chip)
24
. The transmission line
10
may be part of a long bus (e.g., ~10 cm) that ends in two short balanced stubs
16
and
18
(e.g., ~1 cm). When the processor chip
24
is driving (with a driver
12
impedance
14
of ~Zo, matched to the transmission line
10
) it is best to terminate each of the two electrically short stubs
16
and
18
with a termination impedance of ~2Zo such that the parallel combination of the two is ~Zo which gives a good approximation to an ideal terminated transmission line and should yield performance similar to that of a point to point bus. This parallel combination approximation is valid when the length of the stub is much smaller than the length the signal propagates during its rise time.
This arrangement works well in solving the problem associated with a bifurcated transmission line where driving takes place at only the one end. However, cases exist where a chip on one or both of the balanced T stubs wishes to drive the bus. These chips at the terminations of stubs
16
and
18
of
FIG. 1
may be, for example, caches.
In the scheme of
FIG. 1
, with, for example, a processor chip
24
at the long end of transmission line
10
and a first cache chip
20
which is driving the transmission line
10
through stub
16
, it and the second cache chip
22
will both be terminated with an impedance of 2 Zo. However the condition for the parallel combination (that the length of the stub is much smaller than the length the signal propagates during its rise time) is clearly not met since the two chips are very far apart. The essential fact is that the best termination scheme will be different depending on which chip is driving the bus, and this will be true for any non-symmetric bifurcated transmission line network.
Thus, in the example of
FIG. 2
, if the first cache chip
20
is driving the bus, using the prior scheme of having an impedance of Zo at the driving end and an impedances of 2 Zo at the receiving ends, it is clear that of mismatch will result. This then is an non-symmetric transmission line. A transmission line is non-symmetric when the networks response varies according to which device is driving the network.
SUMMARY OF THE INVENTION
In an embodiment of the present invention, a non-symmetric transmission line, having at least three terminations to which chips are coupled, is terminated by dynamically changing termination impedances at the chips according to the topology of the network and which chip is driving the transmission line.
REFERENCES:
patent: 5990701 (1999-11-01), Star
patent: 6029216 (2000-02-01), Hoglund et al.
patent: 6087847 (2000-07-01), Mooney et al.
patent: 6108740 (2000-08-01), Caldwell
patent: 6115773 (2000-09-01), Capps, Jr. et al.
patent: 6118310 (2000-09-01), Esch, Jr.
patent: 6163165 (2000-12-01), Starr
Intel Corporation
Tan Vibol
Tokar Michael
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