Dynamic speed matching of host channel and device data transfers

Details Dynamic speed matching of host channel and device data transfers Dynamic speed matching of host channel and device data transfers

1997-08-28

1999-08-31

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

710 53, 710 57, 711113, 711133, G06F 1314

Patent

active

059448024

ABSTRACT:
The present invention reduces the delay in the completion of transferring data from a data channel to an input/output device and the time a host unit is released from performing the data transfer function. A time reduction is realized by monitoring the current data transfer between the data channel and a buffer device to establish a transfer rate. The transfer rate is used to anticipate and coordinate the transfer of the last bit of data from the data channel to coincide with the receipt of the data by the input/output (I/O) unit, effectively eliminating buffer device delay and allowing the host unit to be released from performing the data transfer. In the preferred embodiment, the transfer of the last bit of data by the data channel occurs at substantially the same time as the last bit of data is received by the I/O unit.

REFERENCES:
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patent: 5566315 (1996-10-01), Milillo et al.
patent: 5696991 (1997-12-01), Chang
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