Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
1998-10-07
2001-05-22
Butler, Dennis M. (Department: 2182)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
Reexamination Certificate
active
06237107
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to output buffers generally and, more particularly, to a dynamic slew rate control output buffer.
BACKGROUND OF THE INVENTION
Complementary output buffers may be used in devices such as the Universal Serial Bus. Conventional approaches to presenting a complementary differential output include implementing two separate differential output drivers. Referring to
FIG. 1
, an output driver
10
is shown receiving an input signal IN and an output driver
12
is shown receiving an input signal INB. The output driver
10
presents a signal A and the output driver
12
presents a signal B. The output drivers
10
and
12
provide a complementary differential output. Since the output driver
10
and the output driver
12
operate independently, it is difficult to inherently match the outputs. Additionally, it may be impractical to produce two sets of output buffers that operate over a wide load and signal swing such as a Universal Serial Bus device.
The output driver
10
is required to provide rising edge circuitry to present the signal A that matches the falling edge circuitry of the output driver
12
to present the signal B. The implementation of separate circuitry results in poor control of parameters like the crossover voltage of the signal A and the signal B and the rise-time/fall-time ratio.
Another solution would be to implement the output drivers
10
and
12
using operational amplifiers. However, operational amplifier drivers are difficult to design to handle large loads with sufficient bandwidth to operate with Universal Serial Bus devices. Additionally, operational amplifier devices may be difficult to design to operate over a wide output swing with a low voltage operation.
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising an output circuit, an adjustment circuit and a detect circuit. The output circuit may be configured to present a first and second output in response to (i) a first and second control signal and (ii) an input signal. The slew rate adjustor circuit may be configured to present the first and second control signals in response to a third control signal. The detect circuit may be configured to present the third control signal in response to the first and second output signals. The slew rate adjuster circuit may dynamically adjust a slew rate of the first and second output signals to minimize common-mode changes.
The objects, features and advantages of the present invention include providing a common-mode circuit that detects movement in a common-mode point that may be used to indicate that the edges are not matching to provide control of (i) the crossover voltage of the outputs, (ii) the rise-time/fall-time ratio and/or (iii) other important factors to devices such as a Universal Serial Bus device.
REFERENCES:
patent: 5424657 (1995-06-01), Brunt et al.
patent: 5592510 (1997-01-01), Brunt et al.
patent: 5675813 (1997-10-01), Holmdahl
patent: 5872473 (1999-02-01), Williams
patent: 5883531 (1999-03-01), Kuo
patent: 6005890 (1999-12-01), Clow et al.
patent: 9736230 (1997-10-01), None
Design Guide for a Low Speed Buffer for the Universal Serial Bus, Revision 1.1, Dec. 1996, Intel Corporation, pp. 1-29.
Universal Serial Bus Specification, Chapter 7—Jan. 15,1996, pp. 111-143.
Snyder Warren S.
Williams Timothy J.
Butler Dennis M.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
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