Dynamic sense amplifier with embedded latch

Details Dynamic sense amplifier with embedded latch Dynamic sense amplifier with embedded latch

1998-02-17

1999-10-05

Nelms, David

Static information storage and retrieval

Read/write circuit

Differential sensing

365202, G11C 702

Patent

active

059634952

ABSTRACT:
A dynamic sense amplifier (10) cooperates with an embedded latch arrangement for converting signals read from a memory cell array to digital signals. The dynamic sense amplifier (10) is connected to a complementary pair of data output lines, each associated with a data output node, and to a complementary pair of data lines from a column decoder associated with the memory cell array. The dynamic sense amplifier (10) is also connected to a sense enable line for receiving a sense enable signal, while the latch incorporated in the dynamic sense amplifier (10) is connected to a latch enable line. The dynamic sense amplifier (10) operates to quickly develop an intermediate charge state at the data output nodes in response to a read charge state on the data lines and a sense enable signal applied at the sense enable line. After developing the intermediate charge state, the latch enable signal is applied to the latch enable line to take the intermediate charge state to a final charge state at the data output nodes. This final charge state at the data output nodes produces data signals on the data output lines. The latch also operates in response to the latch enable signal to hold the charge at the data output nodes, thereby holding the data at the data output lines.

REFERENCES:
patent: 4053873 (1977-10-01), Freeman et al.
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patent: 4751681 (1988-06-01), Hashimoto
patent: 4843264 (1989-06-01), Galbraith
patent: 5204560 (1993-04-01), Bredin et al.
patent: 5526314 (1996-06-01), Kumar
patent: 5783949 (1998-07-01), Reohr et al.
"A 500 MHz 1Mb On-Chip Cache Design Using Multi-Level Bit Line Sensing Scheme" by Richard Guo, et al. (1996 Symposium on VLSI Circuits Digest of Technical Papers) Month Unavailable/ 1996.

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