Dynamic semiconductor storage device

Details Dynamic semiconductor storage device Dynamic semiconductor storage device

2007-12-25

2007-12-25

Yoha, Connie C. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S225700

Reexamination Certificate

active

10553578

ABSTRACT:
To achieve, by a simple circuit configuration, a DRAM that permits refresh current to be effectively reduced by selectively setting refresh cycles. A memory cell array is divided into 64 subarrays, and each subarray is further divided into 8 blocks. A refresh cycle control circuit has a fuse circuit for setting a frequency dividing ratio of 1 or 1/2, a frequency divider that divides the frequency of a predecode signal by the set frequency dividing ratio, fuse circuits for setting a frequency dividing ratio of 1 or 1/4, and frequency dividers for dividing predecode signals by the set frequency dividing ratio. The refresh cycle control circuit is capable of setting a 64-ms or 128-ms refresh cycle for the 64 subarrays and a 64-ms or 256-ms refresh cycle for 512 blocks.

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